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參數(shù)資料
| 型號(hào)： | TP80C51BH-24 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 2/21頁(yè) |
| 文件大?。?/td> | 2233K |
| 代理商： | TP80C51BH-24 |
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87C51/80C51BH/80C31BH
NOTES
:
1. ``Typicals'' are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLs of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specifi-
cation when the address bits are stabilizing.
4. See Figures 6 through 8 for ICC test conditions. Minimum VCC for Power Down is 2V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10 mA
Maximum IOL per 8-bit port-
Port 0:
26 mA
Ports 1, 2, and 3:
15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink greater than the listed test conditions.
272335±26
Figure 5. 87C51/BH ICC vs Frequency
10
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