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參數(shù)資料
| 型號： | TPA5050RSARG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC16 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, QFN-16 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 784K |
| 代理商： | TPA5050RSARG4 |
www.ti.com
SERIAL CONTROL INTERFACE REGISTER SUMMARY
CONTROL REGISTER (0x01)
AUDIO DELAY REGISTERS (0x02–0x05)
FRAME DELAY REGISTERS (0x06)
SLOS492B – MAY 2006 – REVISED MAY 2007
Table 2. Serial Control Register Summary
REGISTER
REGISTER NAME
NO. OF
CONTENTS
INITIALIZATION
BYTES
VALUE
0x01
Control Register
1
Description shown in subsequent section
00
0x02
Right Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x03
Right Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x04
Left Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x05
Left Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x06
Frame Delay
1
Description shown in subsequent section
00
0x07
RJ Packet Length
1
Description shown in subsequent section
00
0x08
Complete Update
1
Description shown in subsequent section
00
The control register allows the user to mute a specific audio channel. It is also used to specify the data type (I2S,
Right-Justified, or Left-Justified.
Table 3. Control Registers (0x01)(1)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
X
–
Left and Right channel are active.
0
1
X
–
Left channel is MUTED.
1
0
X
–
Right channel is MUTED.
1
X
–
Left and Right channel are MUTED.
–
X
0
I2S data format
–
X
0
1
Right-justified data format (see PACKET LENGTH register 0x07)
–
X
1
0
Left-justified data format
–
X
1
Bypass mode – data is passed straight through without delay.
(1)
Default values are in bold.
The audio delay for the left and right channels is fixed by writing a total of 13 bits (2 byte transfer) to upper and
lower registers as specified in Table 1. A multiple byte transfer should be performed starting with the control
register and following with 4 bytes to fill the upper and lower registers associated with right/left channel delay.
The decimal value of D0–D12 equals the number of samples to delay. The maximum number of delayed
samples is 8191 for the TPA5050. This equates to 170.65 ms [8191
× (1/fs)] at 48 kHz.
Table 4. Audio Delay Registers (0x02–0x05)(1)
D12
D11
D10–D2
D1
D0
FUNCTION
0
Left and Right audio is passed to output with no delay.
0
1
Left and Right audio is delayed by 1 sample (1/fs = delay time)
1
Left and Right audio is delayed by 8191 samples (8191/fs = delay time)
(1)
Default values are in bold.
This register can be used to specify delay in video frames instead of audio samples. When the MSB is set to 1,
the audio delay registers (0x01–0x04) are bypassed and the Frame Delay Register is used to set the delay
based on the frame rate (D6), audio sample rate (D5–D3), and number of frames to delay (D2–D0).
The total audio delay time is calculated by the following formula:
Audio Delay (in samples) = int [# Delay Frames
× (1/Frame Rate) × Audio Sample Rate]
10
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TPA5050RSAT | 功能描述:音頻 DSP St Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TPA5050RSATG4 | 功能描述:音頻 DSP St Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TPA5051 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL |
| TPA5051_07 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL |
| TPA5051EVM | 功能描述:音頻 IC 開發(fā)工具 AUD DELAY DEVICE RoHS:否 制造商:Texas Instruments 產品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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