參數(shù)資料
型號： TPS2363PFBG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝： PLASTIC, TQFP-48
文件頁數(shù)： 24/44頁
文件大?。?/td> 840K
代理商： TPS2363PFBG4
SLUS680B – JANUARY 2006 – REVISED JANUARY 2010
www.ti.com
Valid Read Data: (Y corresponds any of the combinations from above)
0Yh – VAUXA/B and main have are not in power good mode.
4Yh – Only the main supplies are in power good mode.
8Yh – Only the VAUXA/B is in power good mode.
cYh – Both VAUXA/Band main are in power good mode.
AUX PG(A/B) (R) : This bit indicates the power good status on the VAUXA/B outputs.
1 – VAUXA/B output is above the power good threshold.
0 – VAUXA/B output is NOT above the power good threshold.
It is set when all of the following conditions are true:
VAUXA/B is enabled through SMBus or direct mode control .
VAUXA/B is above the power good threshold.
The value of this bit is not affected by FORCEONA/B.
MAIN PG(A/B) (R) : This bit indicates the power good status on 3.3 V and 12 V.
1 – The 3.3 V and 12 V outputs are both above their respective power good thresholds.
0 – At least one of the main supplies (3.3 V or 12 V) is not above its power good threshold.
It is set when all of the following conditions are true:
The main supplies are enabled through SMBus or direct mode control.
3.3 V AND 12 V are in above power good threshold.
The value of this bit is not affected by FORCEON INHIBA/B bit.
FORCEON INHIB(A/B) (R/W): This bit is used to inhibit the FORCEONA/B pin.
1 – The FORCEONA/B pin is ignored.
0 – The FORCEONA/B pin can be used.
MAINEN(A/B) (R/W) : This bit controls the main supplies (3.3 V and 12 V).
1 – Enables 3.3 V and 12 V outputs.
0 – Disables 3.3 V and 12 V outputs.
The channel is enabled when this bit is set and all of the following conditions are true:
3.3 V or 12 V not in fault – (Fast trip or over current with timeout or over current with TSHUT1 or UVLO or
TSHUT2).
The AUXINA/B input is above its UVLO threshold.
To reset a fault condition, the bit must be turned off and back on.
AUXEN (A/B) (R/W): This bit controls VAUXA/B output.
1 – Enables the VAUXA/B channel.
0 – Disables the VAUXA/B channel.
Channel A is enabled when this bit is set and the following conditions are true:
VAUXA/B not in fault. (Over current with timeout or over current with TSHUT1 or UVLO or TSHUT2)
The AUXINA/B input is above its UVLO threshold.
To reset a fault condition, the bit must be turned off and back on.
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Copyright 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2363
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