參數(shù)資料
型號(hào)： TPS2383PMR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP64
封裝： GREEN, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 25/28頁(yè)
文件大小： 397K
代理商： TPS2383PMR
TPS2383
SLUS559B APRIL 2003 REVISED JULY 2004
6
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
PIN
I/O
DESCRIPTION
POWER AND GROUND
AG1
26
I
Analog ground 1. Analog ground of the V5, V10 and V48 power systems. It should be externally tied to the
common copper 48-V return plane. This pin should carry the low side of two de-coupling capacitors tied to V48
and V10
AG2
51
I
Analog ground 2. Analog ground, which ties to the substrate and ESD of the device. It should be externally tied
to the common copper 48-V return plane. AG1 and AG2 must be tied together directly for lowest noise
operation.
DG
56
I
Digital ground. It connects to the internal logic ground bus. It should be externally tied to the common copper
48V return plane. In addition a 0.1uF decoupling capacitor should terminate as close to this node and the VL
pin as possible.
RG
29
I
Reference ground. A precision sense of the external ground plane. It should also be used as the ground guard
ring for the integration capacitor (CINT). It should be the closest ground to the low side of the 0.5-
current
sense resistors, as well as RD, CINT, and RT. It should tie to common copper 48-V return plane.
V10
28
O
+10V analog supply.Connects to the internal analog power bus. This voltage is generated internally. This pin
should not be tied to any external supplies. A 0.1-
F de-coupling capacitor should terminate as close to this
node and the AG2 pin as possible. This pin can be used for external generation of V5.
27
I
+48V input to the device. This supply can have a range of 44 V to 57 V. This pin should be de-coupled with a
0.1-
F capacitor from V48 to AG2 placed as close to the device as possible.
V5
25
I
External +5V analog supply.Connects to the internal analog power bus. This supplies the LED output drivers
and internal analog circuits. A 0.1-
F de-coupling capacitor should terminate as close to this node and the AG1
pin as possible.
VL
54
I
External +3.3V logic supply. This pin connects to the internal logic power bus. This is the supply voltage for the
internal device logic. A 0.1-
F de-coupling capacitor should terminate as close to this node and the DG pin as
possible. This pin can be powered from V5 by using a 4.22-k
resistor from V5 to VL..
PORT ANALOG SIGNALS
1P
1
I
2P
8
I
3P
9
I
4P
16
I
Port positive. +48V load sense pin. Terminal voltage is monitored and controlled differentially with respect to nN.
Optionally, if the application warrants it, this high-side path can be protected with the use of a self-resetting poly
5P
33
I
Optionally, if the application warrants it, this high-side path can be protected with the use of a self-resetting poly
fuse.
6P
40
I
fuse.
7P
41
I
8P
48
I
1N
2
I
2N
7
I
3N
10
I
4N
15
I
Port negative. 48V load return sense pin. The low side of the load is switched and protected with the external
5N
34
I
Port negative. 48V load return sense pin. The low side of the load is switched and protected with the external
N-channel MOSFET.
6N
39
I
N-channel MOSFET.
7N
42
I
8N
47
I
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