參數(shù)資料
型號: TPS2383PMR
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP64
封裝: GREEN, PLASTIC, LQFP-64
文件頁數(shù): 27/28頁
文件大小: 397K
代理商: TPS2383PMR
TPS2383
SLUS559B APRIL 2003 REVISED JULY 2004
8
www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
PIN
I/O
DESCRIPTION
DIGITAL SIGNALS
A1
64
I
A2
63
I
Addresses 1 through 5. This is the I2C address select input. Select the appropriate binary address on these pins
A3
62
I
Addresses 1 through 5. This is the I2C address select input. Select the appropriate binary address on these pins
by connecting this pin to device ground for a logic low and tying this pin to the VL pin for a logic high.
A4
61
I
by connecting this pin to device ground for a logic low and tying this pin to the VL pin for a logic high.
A5
60
I
EN
53
I
This pin is normally to be held low. It has been reserved for future expansion of the TPS238x device family
INTB
59
O
This is an open drain output that goes low if a fault condition is produced on any of the eight ports.
PORB
49
I
This pin can be used to override the internal POR. When held low, the I2C interface, all the state machines, and
registers are held in reset. When all internal and external supplies are within specification, and this pin is set to
a logic high level, the POR delay begins. The I2C interface and registers becomes active within eight CLK
periods of this event and communications to read or preset registers can begin. The reset delay for the
remainder of the device then extinguishes within 65536 CLK periods.
SCL_I
55
I
Serial clock input pin for the I2C interface.
SDA_I
58
I
Serial data input pin for the I2C interface. When jumpered with the SDA_O pin, this connection becomes the
standard bi-directional serial data line (SDA).
SDA_O
57
O
Serial data open drain output for the I2C interface. When jumpered with the SDA_I pin, this connection
becomes the standard bi-directional serial data line (SDA). This is a high-voltage open drain output that can
drive opto-coupler LEDs directly from the +48-V bus with an external, series current limiting resistor.
PACKAGE DESCRIPTION
1718 19
8P
8N
8G
8RS
7RS
7G
7N
7P
6P
6N
6G
6RS
5RS
5G
5N
5P
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1P
1N
1G
1RS
2RS
2G
2N
2P
3P
3N
3G
3RS
4RS
4G
4N
4P
21 22 23 24
CR
VL
63 62 61 60 59
64
58
A3
A4
A5
INTB
SDA_I
SDA_O
DG
AG1
V48
V10
RG
L3
L4
L5
L6
L7
L8
V5
56 55 54
57
25 26 27 28 29
53 52
L1
EN
CT
51 50 49
30 31 32
CINT
RT
RD
AG2
SCL_I
PORB
A1
A2
L2
PM PACKAGE
(TOP VIEW)
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