SLVSAL3B
– MARCH 2011 – REVISED MAY 2011
In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of 1.35
V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the
fault timer period, TIMER may go into latch mode (TPS24700) or retry mode (TPS24701).
In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the current-limit threshold following a fast-trip shutdown of M1. When the timer capacitor voltage
reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the
GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24700) or retry
mode (TPS24701).
If the fault current drops below the current limit falling threshold within the fault timer period, VTIMER decreases
and the pass MOSFET, M1, remains enabled.
The behaviors of TIMER are different in the latch mode (TPS24700) and retry mode (TPS24701). If the timer
capacitor reaches the upper threshold of 1.35 V, then:
In latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically until
TPS24700 is disabled by UVLO or EN as shown in
Figure 29.
In retry mode, TIMER charges and discharges CT between the lower threshold of 0.35 V and the upper
threshold of 1.35 V for sixteen cycles before the TPS24701 attempts to restart. The TIMER pin is pulled to
GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial
half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is
removed or the TPS24701 is disabled by UVLO or EN.
OVERTEMPERATURE SHUTDOWN
The TPS24700/1 includes a built-in overtemperature shutdown circuit designed to disable the gate driver if the
die temperature exceeds approximately 140
°C. An overtemperature condition also causes the PGb pin to go to
the high-impedance state. Normal operation resumes once the die temperature has fallen approximately 10
°C.
START-UP OF HOT-SWAP CIRCUIT BY VCC OR EN
The connection and disconnection between a load and the input power bus are controlled by turning on and
turning off the MOSFET, M1.
The TPS24700/1 has two ways to turn on MOSFET M1:
Increasing VVCC above the UVLO upper threshold while EN is already higher than its upper threshold sources
current to the GATE pin. After an inrush period, the TPS24700/1 fully turns on MOSFET M1.
Increasing EN above its upper threshold while VVCC is already higher than the UVLO upper threshold sources
current to the GATE pin. After an inrush period, TPS24700/1 fully turns on MOSFET M1.
The EN pin can be used to start up the TPS24700/1 at a selected input voltage VVCC.
To isolate the load from the input power bus, the GATE pin sinks current and pulls the gate of MOSFET M1 low.
The MOSFET can be disabled by any of the following conditions: UVLO, EN, load current above current limit
threshold, hard short at load, or OTSD. Three separate mechanisms pull down the GATE pin:
1. GATE is pulled down by an 11-mA current source when any of the following occurs.
– The fault timer expires during an overload current fault (VSENSE > 25 mV).
– VEN is below its falling threshold.
– VVCC drops below the UVLO falling threshold.
2. GATE is pulled down by a 1-A current source for 13.5
μs when a hard output short circuit occurs and
V(VCC–SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete,
an 11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20-k
resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
Copyright
2011, Texas Instruments Incorporated
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