參數(shù)資料
型號(hào)： TPS2480PW
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PDSO20
封裝： GREEN, PLASTIC, TSSOP-20
文件頁數(shù)： 27/56頁
文件大?。?/td> 1381K
代理商： TPS2480PW
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P
S
P
www.ti.com
SLUS939B – APRIL 2010 – REVISED DECEMBER 2010
High-Speed I2C Mode
When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates
a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. This
transmission is made in fast (400 kbps) or standard (100 kbps) (F/S) mode at no more than 400 kbps. The
TPS2480/81 does not acknowledge the HS master code, but does recognize it and switches its internal filters to
support 3.4-Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 3.4 Mbps are allowed. Instead of using a stop condition, repeated start conditions should be used
to secure the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the
TPS2480/81 to support the F/S mode.
Figure 24.
Table 3.
FAST MODE
HIGH-SPEED MODE
UNITS
PARAMETER
MIN
MAX
MIN
MAX
f(SCL)
SCL operating frequency
0.001
0.4
0.001
3.4
MHz
T(BUF)
Bus free time between STOP and START condition
600
160
ns
T(HDSTA)
Hold time after repeated START condition. After this period,
100
ns
the first clock is generated.
T(SUSTA)
Repeated START condition setup time
100
ns
T(SUSTO)
STOP condition setup time
100
ns
T(HDDAT)
Data hold time
0
ns
T(SUDAT)
Data setup time
100
10
ns
T(LOW)
SCL clock LOW period
1300
160
ns
T(HIGH)
SCL clock HIGH period
600
60
ns
tF
Clock/data fall time
300
160
ns
tR/ tR
Clock/data rise time clock/data rise time for SCLK
≤ 100kHz
300/1000
160
ns/ns
Power-Up Conditions
Power-up conditions are caused by a software reset via the RST bit (bit 15) in the Configuration Register, or the
I2C bus General Call Reset.
Copyright 2010, Texas Instruments Incorporated
33
Product Folder Link(s): TPS2480 TPS2481
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