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| 型號： | TPS3610U18PWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | 5.10 X 6.60 MM, GREEN, PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大小： | 711K |
| 代理商： | TPS3610U18PWG4 |
TPS3610U18, TPS3610T50
BATTERY BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements at RL = 1 M, CL = 50 pF, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Pulse width
At VDD
VIH = VIT + 0.2 V, VIL = VIT –0.2 V
6
s
tw
Pulse width
At WDI
VDD = VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
100
ns
switching characteristics at RL = 1 M, CL = 50 pF, TA =–40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td
Delay time
VDD > VIT +0.2 V
60
100
140
ms
t(tout) Watchdog timeout
VDD > VIT +0.2 V
(see timing diagram
0.48
0.8
1.12
s
tPLH
Propagation (delay) time, low-to-
high-level output
50% RESET to 50% CEOUT
15
s
VDD = 1.8 V
5
15
50% CEIN to 50% CEOUT,
CF
l (
N
)
VDD = 3.3 V
1.6
5
ns
Propagation (delay) time high-to-
,
CL = 50 pF only (see Note 7)
VDD = 5 V
1
3
ns
tPHL
Propagation (delay) time, high-to-
low-level output
VDD to RESET
VIL = VIT–0.2 V,
VIH = VIT+0.2 V
2
5
s
PFI to PFO
VIL = V(PFI)–0.2 V,
VIH = V(PFI)+0.2 V
3
5
s
tt
Transition time
VDD to BATTON
VIH = VBAT + 200 mV,
VIL = VBAT – 200 mV,
VBAT < VIT
3
s
NOTE 7: Specified by design
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Static drain-source on-state resistance (VDD to VOUT)
vs Output current
6
rDS(on)
Static drain-source on-state resistance (VBAT to VOUT)
vs Output current
7
rDS(on)
Static drain-source on-state resistance
vs Input voltage at CEIN
8
IDD
Supply current
vs Supply voltage
9
VIT
Normalized threshold at RESET
vs Free-air temperature
10
High-level output voltage at RESET
11, 12
VOH
High-level output voltage at PFO
vs High-level output current
13, 14
VOH
High-level output voltage at CEOUT
vs High level out ut current
15, 16, 17, 18
Low-level output voltage at RESET
19, 20
VOL
Low-level output voltage at CEOUT
vs Low-level output current
21, 22
VOL
Low-level output voltage at BATTON
vs Low level out ut current
23, 24
tp(min)
Minimum Pulse Duration at VDD
vs Threshold overdrive at VDD
25
tp(min)
Minimum Pulse Duration at PFI
vs Threshold overdrive at PFI
26
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| TPS3610U18PWR | 功能描述:監(jiān)控電路 Battery-Backup for RAM Retention RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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