參數(shù)資料
型號(hào)： TPS40042DRCTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 700 kHz SWITCHING FREQ-MAX, PDSO10
封裝： 3 X 3 MM, GREEN, PLASTIC, SON-10
文件頁(yè)數(shù)： 34/35頁(yè)
文件大?。?/td> 746K
代理商： TPS40042DRCTG4
www.ti.com
DEVICE INFORMATION
TERMINAL CONFIGURATION
1
2
3
4
10
9
8
7
HDRV
SW
BOOT
LDRV
EN
FB
COMP
VDD
6
GND
5
REFIN
SLUS777 – NOVEMBER 2007
The package is an 10-pin SON (DRC) package.
Figure 13. DRC Package Terminal Configuration (Top View)
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Input (bootstrapped) supply to the high-side gate driver for PWM enabling the gate of the
high side FET to be driven above the input supply rail. Connect a ceramic capacitor from this
pin to SW. This capacitor is charged from the VDD pin voltage through an internal switch.
BOOT
8
I
The switch is turned ON during the off time of the converter. To slow down the turn on of the
external MOSFET, a small resistor (1
to 3 ) may be placed in series with the bootstrap
capacitor. See Applications Section to calculate the appropriate value.
Output of the error amplifier and connection node for loop feedback components. The
voltage at this pin determines the duty cycle for the PWM. Optionally, a resistor from this pin
to ground is used to determine the voltage threshold used for short circuit protection. (See
Application Section)
COMP
4
O
Low threshold R = 2.4 k
, ±10%
Mid threshold R = not installed
High threshold R = 12 k
, ±10%
Active low enable input allows ON/OFF operation of the controller. If power is applied to the
TPS40042 while the EN pin is allowed to float high, the TPS40042 remains disabled (both
EN
2
I
external switches are held OFF). Only when the EN pin is pulled to 1.2 V below VDD is the
TPS40042 allowed to start. An internal 100-k
resistor is connected between VDD and EN
to provide pull up. Connect this pin to GND to bypass the enable function.
Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is at the
same potential as the REFIN pin. A series resistor divider from the converter output to
FB
3
I
ground, with the center connection tied to this pin, determines the value of the regulated
output voltage. This pin is also a connection node for loop feedback components.
GND
6
Electrical ground connection for the device.
This is the gate drive output for the high side N-channel MOSFET switch for PWM. It is
HDRV
10
O
referenced to SW and is bootstrapped for enhancement of the high-side switch.
LDRV
7
O
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET.
Non-inverting imput to the error amplifier. A precision voltage must be applied to this pin
before the TPS40042 is enabled. Since this input is connected directly to the non-inverting
REFIN
1
I
pin of the error amplifier, the quality of the voltage at this pin has a direct impact on the
quality of the output voltage.
Connection to the switched node of the converter and the power return for the upper gate
driver. There should be a high current return path from the source of the upper MOSFET to
SW
9
O
this pin. It is also used by the adaptive gate drive circuits to minimize the dead time between
upper and lower MOSFET conduction.
Power input to the device. This pin should be locally bypassed to GND with a low ESR
VDD
5
I
ceramic capacitor of 1
F or greater.
Thermal pad used to conduct heat from the device. This pad should be tied externally to a
PPAD
ground plane. See Application Section for PC board layout information.
8
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
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