VDG03174
tBLANKING
7 Current-Limit Trips
(HDRV Cycle Terminated by Current-Limit Trip)
7
Soft-Start
Cycles
HDRV
Clock
VILIM
VVIN VSW
SS
LOOP COMPENSATION
K
PWM ^ VUVLO (on)
(14)
www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
Figure 11. Typical Fault Protection Waveforms
Voltage mode buck type converters are typically compensated using Type III networks. Since the TPS4007x
uses voltage feedforward control, the gain of the voltage feedforward circuit must be included in the PWM gain.
The gain of the voltage feedforward circuit combined with the PWM circuit and power stage for the TPS4007x is:
The remainder of the loop compensation is performed as in a normal buck converter. Note that the voltage
feedforward circuitry removes the input voltage term from the expression for PWM gain. PWM gain is strictly a
function of the programmed startup voltage.
Copyright 2003–2009, Texas Instruments Incorporated
15