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Overvoltage Protection, Non-Latching
Output Undervoltage Protection
Programmable Input Undervoltage Lockout Protection
Power-On Reset (POR)
Fault Masking Operation
Fault Conditions and MOSFET Control
SLVS635 – FEBRUARY 2007
FUNCTIONAL DESCRIPTION (continued)
If the overcurrent condition persists, both phases have PWM cycles terminated by the overcurrent signals. This
puts a converter in a constant current mode with the output current programmed by the ILIM voltage. A counter
is incremented for each PWM cycle in which an overcurrent event is detected. The counter is reset every 32
PWM cycles. If the counter accumulates a count of 7 before being reset, the converter enters a hiccup mode.
The HDRV and LDRV signals are set low during the hiccup mode.
The SS capacitor serves as a hiccup timing capacitor controlled by U20, the fault control circuit. The soft-start
pin is periodically charged and discharged by U20. After seven hiccup cycles, the controller attempts another
soft-start cycle to restore normal operation. If the overload condition persists, the controller returns to the hiccup
mode. This condition may continue indefinitely. In such conditions the average current delivered to the load is
approximately 1/8 of the set overcurrent value.
The voltage on OVSET is compared with 0.817 V, 16% higher than VREF, in U25 to determine the output
overvoltage point. When an overvoltage is detected, the output drivers command the upper MOSFETs off and
the lower MOSFETs on. If the overvoltage condition has been cleared, the output comes up and normal
operation continues. Turning the lower MOSFET on may cause the output to reach an undervoltage condition
and enter the hiccup mode. Using a voltage divider with the same ratio, that sets the output voltage, an output
overvoltage is declared when the output rises 16% above nominal.
If the output voltage, as sensed by U19 on the FB pin becomes less than 0.588 V, the undervoltage protection
threshold (84% of VREF), the controller enters the hiccup mode.
A voltage divider that sets 1V on the UVLO pin determines when the controller starts operating. Operation
commences when the voltage on the UVLO pin exceeds 1.0 V. If the voltage on the UVLO pin falls to 0.81 V,
the controller is turned off and the HDRV and LDRV signals are set low.
The power-on reset (POR) function, U22, insures the VIN5 and BP5 voltages are within their regulation windows
before the controller is allowed to start.
If the SS pin voltage is externally limited below the 1-V threshold, the controller does not respond to most faults
and the PGOOD output is always low. Only the overcurrent function remains active. The overcurrent protection
still continues to terminate PWM cycle every time when the threshold is exceeded but the hiccup mode is not
entered.
Table 1 shows a summary of the fault conditions and the state of the MOSFETs.
Table 1. Fault Condifions
FAULT MODE
UPPER MOSFET
LOWER MOSFET
EN/SYNC = LOW
OFF
FIXED UVLO, VBP5 < 4.25 V
OFF
Programmable UVLO, < 1.0 V
OFF
Output undervoltage
OFF, Hiccup mode
Output overvoltage
OFF
ON
Output overcurrent
OFF, Hiccup mode
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