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Layout Guidelines
www.ti.com .................................................................................................................................................. SLUS843B – MAY 2008 – REVISED SEPTEMBER 2008
1. Place one or two 10-
F ceramic capacitor(s) for V
IN between two channels. Add 1000-pF ceramic capacitor
between drain of the high-side MOSFET and source of the low-side MOSFET of each channel.
2. Place VIN capacitors, VOUT1/VOUT2 capacitors and MOSFETs on the same side of the board. Positive
terminal of VIN capacitor and drain of the high-side MOSFET should be as close as possible (within 10 mm if
possible). Also place negative terminals of both VIN capacitor and VOUT capacitor, and source of the low-side
MOSFET as close as possible.
3. GND terminal of the device (signal GND) and PGND terminal (power GND) should be connected with the
lowest impedance near the device.
4. Trace of the switching node which is connected between the source of the high-side MOSFET, drain of the
low-side MOSFET and the upstream of the output inductor should be as short and thick as possible. Use 40
mil of width (LL1 and LL2) for every ampere of load current.
5. LL1 and LL2 serve the phase node connections for the high-side drivers. Also, they are served as input to
the current comparators for RDS(on) sensing and input voltage monitor for the on time control circuitry. Route
the return of these two traces to device pins as wide and short as possible to eliminate the parasitic
inductance effect to the accuracy of the measurement.
6. Place a low-pass filter MLCC capacitor with a value of 1-
F from V5FILT to GND, as close as possible.
7. The output of LDO if configured as 5VLDO, requires at least 4.7-
F of MLCC to GND. If it is configured as
3.3 VLDO, 10
F of MLCC is recommended. For optimized stability and transient response, use a value of
27
F if the output of LDO is configured as 1VLDO. VREF2 requires 0.1-F ceramic bypass capacitor to
GND which should be placed as close to the device as possible. For VREF3, it generally requires a 1-
F
ceramic by pass capacitor to GND which also should be placed as close to the device as possible.
8. Connect the overcurrent setting resistors from TRIP1/TRIP2 to GND. The traces from TRIP1/TRIP2 should
be routed as far as possible from the switching nodes.
9. 9. In the case of adjustable output voltage with external resistor dividers, the discharge path (VOx) can share
the trace to the output capacitor with the feedback trace (VFB1/REFIN2). Please place the voltage setting
resistors as close to the device as possible. Route the VOx and feedback traces as far from the high speed
switching nodes as possible to avoid noise coupling.
10. Connections from the drivers to the respective gate of the high-side or the low-side MOSFETs should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace.
11. All sensitive analog traces and components such as VO1/VO2, VFB1/REFIN2, VREF2, VREF3, EN1/EN2,
GND, VSW, PGOOD1/PGOOD2, TRIP1/TRIP2, ENLDO, LDOREFIN, V5FILT, TONSEL and SKIPSEL
should be placed away from high-voltage switching nodes such as LLx, DRVLx or DRVHx nodes to avoid
coupling. Use internal layer(s) as ground plane(s) and shield feedback traces from power traces and
components.
12. In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. 3 × 3 or more vias with a 0.33-mm (13mils) diameter connected from the thermal land to the
internal ground plane should be used to help dissipation. Connect GND to the thermal land directly.
Copyright 2008, Texas Instruments Incorporated
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