
ENABLE AND SOFT START
POWER-GOOD
OUTPUT SHUTDOWN AND DISCHARGE CONTROL
2-V REFERENCE (VREF2)
3-V REFERENCE (VREF3)
SLUS843B – MAY 2008 – REVISED SEPTEMBER 2008 .................................................................................................................................................. www.ti.com
Table 2. TONSEL Terminal Connection Options
TONSEL
GND
VREF2 or Float
V5FILT
Channel1 Frequency
400 kHz
200 kHz
Channel2 Frequency
500 kHz
300 kHz
TPS51427A has an internal digital soft-start timer that begins to ramp up to the maximum allowed current limit
during device startup. The soft-start ramp occurs in five steps of positive current limit; step sizes are 20%, 40%,
60%, 80%, and 100%. Smooth control of the output voltage during device startup is maintained. In addition, if
tracking discharge is required, the ENx pin can be used to control the output voltage discharge smoothly. At the
beginning of the soft-start period, the rectifying MOSFET maintains an off state until the top MOSFET turns on at
least once. This architecture prevents a high negative current from flowing back from the output capacitor in the
event of an output capacitor pre-charged condition.
If EN1 is connected to VREF2, Channel1 starts up after the Channel2 reaches regulation (delay start). If EN2 is
connected to VREF2, Channel2 starts up after the Channel1 reaches regulation (delay start).
When both ENx are low and ENLDO is low, the TPS51427A enters a shutdown state and consumes less than
15
A.
The TPS51427A has a power-good output (PGOODx) for each switching channel. The power-good function
activates after the soft start finishes. If the output voltage reaches within ±95% of the target value, internal
comparators detect a power-good state and the power-good signal goes high after a 1-ms internal delay. If the
output voltage falls below 90% of the target value, the power-good signal goes low after a 10-
s internal delay.
The TPS51427A discharges the output when ENx is low, or when the controller is shut down by the circuit
protection functions (OVP, UVP, UVLO, and thermal shutdown). The TPS51427A discharges the outputs using
an internal, 17-
MOSFET that is connected to VOUTx and PGND. The external low-side MOSFET does not
turn on during the output discharge operation to avoid the possibility of causing a negative voltage at the output.
The output discharge time constant is a function of the output capacitance and the resistance of the internal
discharge MOSFET. This discharge ensures that on device restart, the regulated voltage always starts from 0 V.
If an SMPS restarts before the discharge completes, the discharge action is terminated and switching resumes
after the reference level (ramped up by an internal digital-to-analog converter, or DAC) returns to the remaining
output voltage. When shutdown mode activates, the 3.3-V VREF3 remains on.
The 2-V reference is useful for generating auxiliary voltages. The tolerance for this reference voltage is ±1.25%
over a 50-
A load and –40°C to +85°C ambient temperature range. This reference is enabled when ENLDO
goes high, and shuts down after both switching channels are turned off and ENLDO is shut down. If this output is
forcibly tied to ground, both SMPSs are turned off without a latch. Bypass the VREF2 pin to GND with a
minimum 0.1-
F ceramic capacitor.
The 3.3-V reference (VREF3) is accurate to ±1.5% over temperature, making VREF3 useful as a precision
system reference for the real-time clock (RTC) circuit in many notebook applications. VREF3 can supply up to 10
mA for external loads. Bypass VREF3 to GND with a 1-
F capacitor. VREF3 is activated when VIN rises above
2.1 V, and remains on even when the SMPS and LDO are both shut down. VREF3 is deactivated if VIN falls
below 1.8 V. In thermal shutdown conditions, VREF3 remains activate.
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Copyright 2008, Texas Instruments Incorporated