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參數(shù)資料
| 型號： | TPS53851RHHT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, PQCC36 |
| 封裝： | PLASTIC, VQFN-36 |
| 文件頁數(shù)： | 6/66頁 |
| 文件大小： | 1264K |
| 代理商： | TPS53851RHHT |
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SLUS985 – DECEMBER 2009
www.ti.com
Table 4-1. TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Power good indicators for CH1 output voltage. This open-drain output connects to a voltage via an
PGOOD1
30
O
external resistor
Power good indicators for CH2 output voltage. This open-drain output connects to a voltage via an
PGOOD2
15
O
external resistor
A 20
μA current flows from this pin. In a single controller design, this pin should be grounded. In a multi
PHSEL
4
O
controller configuration, a 39- k
resistor string sets the voltage on this pin determines the proper phasing
for the slaves. See the section on ' CLOCK MASTER, PHSEL AND CLKIO CONFIGURATIONS'
RT
5
I
Connecting a resistor from this pin to ground sets the oscillator frequency.
Connect to the switched node on converter CH1. It is the return for the CH 1 upper gate driver. There
should be a high current return path from the source of the upper MOSFET to this pin. This pin is also
SW1
25
I
used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET
conduction.
Connect to the switched node on converter CH2. It is the return for the CH 2 upper gate driver. There
should be a high current return path from the source of the upper MOSFET to this pin. This pin is also
SW2
20
I
used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET
conduction.
This is an input to the non-inverting input of the error amplifier CH1. This pin is normally connected to the
TRK1
33
I
soft-start capacitor or to another voltage that is tracked.
This is an input to the non-inverting input of the error amplifier CH2. This pin is normally connected to the
TRK2
12
I
soft-start capacitor or to another voltage that is tracked.
A voltage divider from VIN to this pin determines the input voltage that CH1 starts. When the voltage is
UVLO_CE1
29
I
between 0.5 V and 1.5 V the VREG regulator is enabled . When the voltage is 2.1 V or above CH1 soft
start is allowed to begin.
A voltage divider from VIN to this pin determines the input voltage that CH2 starts. When the voltage is
UVLO_CE2
16
I
between 0.5 V and 1.5 V the VREG regulator is enabled . When the voltage is 2.1 V or above CH2 soft
start is allowed to begin.
Power input for the controller 5-V regulator and differential amplifier. A 1.0-
μF ceramic capacitor should
VDD
17
I
be connected from this pin to ground.
Non-inverting input of the differential amplifier. This pin should be connected to the output of the converter
VOUT
2
I
close to the load point. If the differential amplifier is not used, leave this pin open.
The output of the internal 5-V regulator. A 4.7-
μF ceramic capacitor should be connected from this pin to
VREG
21
O
PGND.
VSHARE
6
O
The 1.8-V reference output.
14
DEVICE INFORMATION
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS53851
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