參數(shù)資料
型號: TPS65011RGZT
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48
封裝: 7 X 7 MM, PLASTIC, QFN-48
文件頁數(shù): 31/57頁
文件大小: 1414K
代理商: TPS65011RGZT
www.ti.com
SYSTEM RESET AND CONTROL SIGNALS
VIBRATOR DRIVER
LED2 OUTPUT
INTERRUPT MANAGEMENT
TPS65011
SLVS501A – FEBRUARY 2004 – REVISED JANUARY 2005
The RESPWRON signal is used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the Power Good comparator linked to VMAIN and remains low for
tn(RESPWRON) seconds after VMAIN has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET and INT
are also held low.
If the output voltage of MAIN is less than 90% of its nominal value, as RESPWRON is generated, and if the
output voltage of MAIN is programmed to a higher value, which causes the output voltage to fall out of the 90%
window, then a RESPWRON signal is generated.
The PWRFAIL signal indicates when VCC < UVLO or when the TPS65011 junction temperature has exceeded a
reliable value or if BATT_COVER is taken low. This open drain output can be connected at a fast interrupt pin for
immediate attention by the application processor. All supplies are disabled t(uvlo), t(overtemp) or t(batt_cover) seconds
after PWRFAIL has gone low, giving time for the application processor to shut down cleanly.
BATT_COVER is used to detect whether the battery cover is in place or not. If the battery cover is removed, the
TPS65011 generates a warning to the processor that the battery is likely to be removed and that it may be
prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER
pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER
has an internal 2-M
pulldown resistor.
The HOT_RESET input is used to generate an MPU_RESET signal for the application processor. The
HOT_RESET pin could be connected to a user-activated button in the application. It can also be used to exit low
power mode. In this case, the TPS65011 waits until the VCORE voltage has stabilized before generating the
MPU_RESET pulse. The MPU_RESET pulse is active low for t(mpu_nreset) seconds. HOT_RESET has an internal
1-M
pullup resistor to V
CC.
The PB_ONOFF input can be used to exit LOW POWER MODE. It is typically driven by a user-activated
push-button in the application. Both HOT_RESET and PB_ONOFF are de-bounced internally by the TPS65011.
Typical de-bounce time is 56 ms. PB_ONOFF has an internal 1-M
pulldown resistor.
PB_ONOFF, BATT_COVER and UVLO events also cause a normal, maskable interrupt to be generated and are
noted in the REGSTATUS register.
The VIB open-drain output is provided to drive a vibrator motor, controlled via the serial interface register
VDCDC2. It has a maximum dropout of 0.5 V at 100-mA load. Typically, an external resistor is required to limit
the motor current, and a freewheel diode to limit the VIB overshoot voltage at turnoff.
The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off.
The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum
blink-on time is 10 ms and this can be increased in 127 10-ms steps to 1280 ms. For both PG and LED2, the
minimum blink period is 100 ms and this can be increased in 127 100-ms steps to 12800 ms.
The open-drain INT pin is used to combine and report all possible conditions via a single pin. Battery and chip
temperature faults, precharge timeout, charge timeout, taper timeout, and termination current are each capable
of setting INT low, i.e., active. INT can also be activated if any of the regulators are below the regulation
threshold. Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can
be programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to
mask an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2,
or MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS,
REGSTATUS, and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are
acknowledged by reading these registers. If a 1 is present in any location, then the TPS65011 automatically sets
the corresponding bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register
contents are self-clearing when the condition, which caused the interrupt, is removed. The applications processor
should not normally need to access the ACKINT1 or ACKINT2 registers.
37
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