參數(shù)資料
型號： TPS65055RSMR
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 1.8 A DUAL SWITCHING CONTROLLER, 2475 kHz SWITCHING FREQ-MAX, PQCC32
封裝： 4 X 4 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 19/41頁
文件大?。?/td> 1276K
代理商： TPS65055RSMR
SLVS844 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
Bit 0
FPWM DCDC2:
0 = DCDC2 converter operates in PWM / PFM mode
1 = DCDC2 converter is forced into fixed frequency PWM mode
CON_CTRL2. Register Address: 04h (read/write)
Default Value: 0Fh
CON_CTRL2
B7
B6
B5
B4
B3
B2
B1
BO
Bit name and function
GO
DCDC1
DCDC2
LDO1
LDO2
LDO3
LDO4
discharge
Default
0
1
Default value loaded by:
UVLO +
UVLO
DONE*
Read/write
R
R/W
The CON_CTRL2 register can be used to take control of the inductive converters.
Bit 7
GO:
0 = No change in the output voltage for the DCDC2 converter
1 = A voltage change for the DCDC2 converter is ongoing. The voltage is changed to the value written
into the DEFDCDC2_HIGH or DEFDCDC2_LOW register with the slew rate defined in DEFSLEW.
This bit is automatically set and cleared internally. The transition is considered complete in this case
when the desired output voltage code has been reached, not when the VDCDC2 output voltage is
actually in regulation at the desired voltage. The GO bit is also high when a voltage change is ongoing
caused by changing the logic level of the DEFDCDC2 pin.
Bit 5–0 0 = The output capacitor of the associated converter or LDO is not actively discharged when the
converter or LDO is disabled
1 = The output capacitor of the associated converter or LDO is actively discharged when the converter
or LDO is disabled. This decreases the fall time of the output voltage at light load
DEFDCDC2_LOW. Register Address: 05h (read/write)
Default Value: 10h
DEFDCDC2_LOW
B7
B6
B5
B4
B3
B2
B1
BO
Bit name and function
DCDC2[5]
DCDC2[4]
DCDC2[3]
DCDC2[2]
DCDC2[1]
DCDC2[0]
Default
0
1
0
Default value loaded by:
UVLO
Read/write
R
R/W
DEFDCDC2_HIGH. Register Address: 06h (read/write)
Default Value: 08h
DEFDCDC2_HIGH
B7
B6
B5
B4
B3
B2
B1
BO
Bit name and function
DCDC2[5]
DCDC2[4]
DCDC2[3]
DCDC2[2]
DCDC2[1]
DCDC2[0]
Default
0
1
0
Default value loaded by:
UVLO
Read/write
R
R/W
The output voltage for DCDC2 is switched between the value defined in DEFDCDC2_LOW and
DEFDCDC2_HIGH depending on the status of the DEFDCDC2 pin. IF DEFDCDC2 is low, the value in
DEFDCDC2_LOW is selected, if DEFDCDC2 = high, the value in DEFDCDC2_HIGH is selected.
Table 1. VOLTAGE TABLE FOR DCDC2
OUTPUT VOLTAGE
B5
B4
B3
B2
B1
B0
[V]
0
0.800
0
1
0.825
0
1
2
0.850
0
1
0
26
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65055
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