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參數(shù)資料
| 型號： | TPS65200YFFR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, BGA36 |
| 封裝： | 2.80 X 2.60 MM, 0.40 MM PITCH, GREEN, DSBGA-36 |
| 文件頁數(shù)： | 36/59頁 |
| 文件大小： | 2424K |
| 代理商： | TPS65200YFFR |
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Place C9 and
C10 (VSYS) as
close to L2 as
possible with
short connection
to ground.
Place C2 and C3
as close to the IC
as possible.
Connection C2-
[A3] and C3-[A2]
must not be in
any current path
and should be
kept as short as
possible. Traces
should connect
directly to sense
resistor R5.
Pins [A1] and
[A2] must not be
shorted at the IC
but routed
separately to R5.
Keep [C1], [C2],
[C3] (SWC) to L2
Keep C6-[E6]
trace shielded
from SWL node
to avoid noise
coupling.
Place L1 as
close to the IC as
possible. Keep
traces between
L1, D1 and [F6]
short and wide.
Max trace current
is 700mA.
Place C1 close to
D1 and keep
trace short and
Place C8 as
close to the IC as
possible. Max
trace current is
60mA.
Place input
capacitor C7
(VBUS) as close
C4 should be
placed close to
the IC.Trace
current is low
<1mA.)
Place C12
(PMID) as close
to the IC as
possible. Max
trace current is
Keep [C1], [C2],
[C3] (SWC) to L2
connection short
and wide. Adding
vias is OK. Max
trace current is
2A.
Keep VSYS to L1
connection short
and wide. Max
trace current is
700mA.
www.ti.com
SLVSA48 – APRIL 2010
Figure 60. TOP: Top Layer PCB Layout. BOTTOM: Bottom Layer PCB Layout.
Copyright 2010, Texas Instruments Incorporated
41
Product Folder Link(s): TPS65200
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