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參數(shù)資料
| 型號(hào)： | TQ2059 |
| 廠商： | TriQuint Semiconductor,Inc. |
| 英文描述： | High-Frequency Clock Generator |
| 中文描述： | 高頻時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大小： | 195K |
| 代理商： | TQ2059 |
TQ2059
4
For additional information and latest specifications, see our website:
www.triquint.com
Symbol
Input Clock (REFCLK)
Test Conditions
Min
Typ
Max
Unit
t
CPWH
t
CPWL
t
IR
CLK pulse width HIGH
CLK pulse width LOW
Input rise time
(0.8 V – 2.0 V)
Figure 2
Figure 2
4
4
—
—
—
—
—
—
2.0
ns
ns
ns
Figure 2
Figure 1
Symbol
Input Clock (REFCLK)
Test Conditions
Min
Typ
Max
Unit
t
OR,
t
OF
t
CYC
t
JP2
t
SYNC3
Rise/fall time (20% – 80%)
Duty-cycle
Period-to-Period Jitter
Synchronization Time
Figure 2
Figure 2
100
45
—
—
220
50
30
10
350
55
120
500
ps
%
ps
μ
s
AC Characteristics (V
DD
= +5 V
+ 5%, T
A
= 0
°
C to +70
°
C)
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. Jitter specification is peak to peak. Period-to-Period jitter is the jitter on the output with respect to the output's previous crossing.
3. t
SYNC
is the time required for the PLL to synchronize and assumes the presence of a CLK signal.
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