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參數(shù)資料
| 型號： | TQ6124 |
| 廠商： | TriQuint Semiconductor,Inc. |
| 英文描述： | 1 Gigasample/sec, 14-bit Digital-to-Analog Convertor |
| 中文描述： | 1 Gigasample /秒，14位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 177K |
| 代理商： | TQ6124 |
TQ6124
3
For additional information and latest specifications, see our website:
www.triquint.com
M
P
Electrical Specifications
Table 1. Recommended Operating Conditions
Symbol
Parameter
Min.
Nom.
Max.
Unit
V
SS
V
AA
T
C
Negative Power Supply
Analog Power Supply
Case Temperature
–5.25
–15.5
–20
–5.0
–12
–4.75
–11.5
85
V
V
°
C
Table 2. DC Operating Characteristics
Unless otherwise specified, measured over Recommended Operating Conditions with balanced 50
loads, V
FS
= 1.0 V.
Symbol
Parameter
Condition
Min.
Nom.
Max.
Unit
I
AA
I
SS
V
REF
I
REF
V
IH
V
IL
I
I
V
EREF
R
EREF
DNL
INL
V
AA
Supply Current
V
SS
Supply Current
Reference Voltage
Reference input current
ECL Input High Voltage
ECL Input Low Voltage
ECL Input Current
ECL Reference Voltage
ECL Reference Resistance
Differential non-linearity
Integral non-linearity
Full-scale symmetry
Full-scale output voltage
V
O
, NV
O
, output resistance
R
OUT
Matching
Output Voltage
Zero Scale Voltage
Sense output voltage
Thermal Impedance
–75
–285
V
AA
+ 3.0
–90
–450
V
AA
+ 3.75
25
–0.6
–1.5
25
mA
mA
V
mA
V
V
mA
V
ohms
%F.S.
%F.S.
mV
V
ohms
%
V
mV
V
°
C/W
V
AA
+ 2.5
–25
–1.1
–2.5
–25
V
EREF
= –1.3 V
V
EREF
= –1.3 V
V
SS
= –5.0 V
–1.34
400
0.026
0.035
2
–1.0
50.9
0.15
(Note 2)
(Note 2)
(Note 1)
R
L
= 50 ohms
–0.05
–0.05
–8
0.05
0.05
8
–1.125
57
2.5
0
0
V
AA
+ 3.75
V
FS
R
OUT
44
–2.5
–1.125
–50
V
AA
+ 2.5
V
O
, NV
O
V
ZS
V
SENSE
θ
JC
–40
15
Notes: 1. Full-scale symmetry is a measure of the balance between V
O
and NV
O
. For a full-scale output transition,
the change in V
O
will match the change in NV
O
to within the specified amount. Any imbalance in the
output loads will affect symmetry.
2. Linearity can interpreted as 10 bits at
1
/
2
LSB or as 11 bits at 1 LSB. The device is monotonic to 10 bits.
Linearity is tested with the Mid_trim set for optimal DNL, with the LSB_trim pin open.
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