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參數(shù)資料
| 型號： | TQ6124 |
| 廠商： | TriQuint Semiconductor,Inc. |
| 英文描述： | 1 Gigasample/sec, 14-bit Digital-to-Analog Convertor |
| 中文描述： | 1 Gigasample /秒，14位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 177K |
| 代理商： | TQ6124 |
TQ6124
7
For additional information and latest specifications, see our website:
www.triquint.com
M
P
Table 5. Signal-Pin Descriptions
Signal
Pin(s)
Description
DGND
AGND
D
0
thru D
13
6, 7, 8, 28, 29, 37, 40
13, 15, 18, 19
30, 31, 32, 35, 36, 38, 39,
41, 42, 43, 2, 3, 4, 5
17, 16
9, 10
14
20
21
1, 11, 12, 33, 34, 44
22, 23, 24
25
26
27
Ground connection for digital circuitry.
Ground connection for analog circuitry.
Data inputs. D
0
is the least significant bit. ECL levels.
V
O
, NV
O
CLK, NCLK
I
REF
V
SENSE
V
REF
V
SS
V
AA
Mid_trim
LSB_trim
ECLref
True and complementary analog outputs.
True and complementary clock inputs. ECL levels.
Connect to AGND. Source of dummy currents in the switch array.
Sense Output.
Reference Input.
Digital negative power supply.
Analog negative power supply.
Trim terminal for mid range bits.
Trim terminal for LSB range bits.
Optional ECL reference level adjustment. Thevinin equivalent is 1.3V
nominally into 400 ohms. Equivalent voltage tracks with digital supply.
Typical Performance Data
The graph in Figure 7 shows representative
performance data of spurious free dynamic range
(SFDR) vs. output frequency performance measured
from TQ6124 devices.
Data was collected at room temperature; note,
however, that SFDR is not strongly dependendent on
temperature. Optimum performance is obtained by
utilizing as high a clock rate as practical.
Figure 7. SFDR vs. Output Frequency
–30
–35
–40
–45
–50
–55
–60
–65
50
100
150
200
250
F
OUT
300
350
400
450
500
0
SFDR
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