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參數(shù)資料
| 型號： | TQ8223 |
| 英文描述： | ATM/SONET Demultiplexer |
| 中文描述： | ATM機/ SONET的多路解復用器 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 210K |
| 代理商： | TQ8223 |
16
TQ8223
PRELIMINARY DATA SHEET
Signal
CK78T
Symbol
tckdc
tckr
tckf
Voh
Vol
Cload
Description
Output clock duty cycle (Note 3)
Output clock rise time (20% to 80%)
Output clock fall time (20% to 80%)
Output clock high level
Output clock low level
Output load capacitance
Output data delay 1 (Note 1)
Output data hold time (Note 1)
Output high voltage (Note 2)
Output low voltage (Note 2)
Output high-level output current
Output low-level output current
Output load capacitance
Min
40
Nom
50
Max
60
2000
2000
V
DD
0.4
Units
%
ps
ps
V
V
pF
ns
ns
V
V
mA
mA
pF
2.4
V
EE
20
RQ11-18 Tpd1
RQ21-28 Tpd2
RQ31-38 Voh
RQ41-48 Vol
RQPAR1
RQPAR2
RQPAR3
RQPAR4
LOCK
LOCKREF Vih
PPMSEL
MODE(0:1)
PARSEL
1.8
0
V
DD
0.4
2.4
V
EE
Ioh
Iol
Cload
50
-20
20
Input high level
Inputt low level
2.0
V
EE
V
DD
0.8
V
V
Vil
Notes:
1.See Figure 6. Tpd1 and Tpd2 are specified relative to the falling edge of the CK78T signal. Output data edge jitter is not included in
the specifications. The output data streams are assumed to be free of any skewing in time. The specifications apply under the
following conditions:
Output data rise/fall time:
<= 2000ps (20% to 80%)
Output data:
2
23
-1 PRBS, 32x78Mb/s
Output clock frequency:
77.76MHz
2.Output data level requirements apply under the following conditions:
Output data:
2
23
-1 PRBS, 32x78Mbit/s
Output clock frequency:
77.76MHz
3.Output clock duty cycle is measured at the mean voltage of the signal and nominal input clock frequency of 2.48832GHz.
Table 12. TTL Interface Specifications
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