參數(shù)資料
型號(hào)： TQ8224
英文描述： Industrial Control IC
中文描述： 工業(yè)控制IC
文件頁(yè)數(shù)： 5/22頁(yè)
文件大?。?/td> 210K
代理商： TQ8224
TQ8223
PRELIMINARY DATA SHEET
5
S
P
T
P
Internal Clock VCO and External PLL
See
Figure 9
for a reference diagram of operation with
the internal clock and external PLL. PHREF and DCREF
must be connected to an external integrator. The output
of the integrator is then connected to VTUNE,
completing the PLL.
Output Clocks
The TQ8223 provides an internal Clock Divider which
frequency divides the active 2.48832 GHz
clock
(internal or external source as selected by CLKSEL).
The output of the Clock Divider supplies the internal
clock signals necessary for the re-timing function and
demultiplexing function. Clock Divider block also
outputs
four external clocks: a differential 311.04 MHz
PECL clock at
CK311 and NCK311,
a 155.52MHz PECL
clock at CK155, a
77.76 MHz TTL clock at CK78T,
and a
38.88 MHz PECL clock at CK39. Note that the clock
frequencies given above are dependant upon using the
part at 2.48832 GHz.
Data Demultiplexer and Parity Generator
The TQ8223 can be configured to run in one of two
modes. The demultiplexing modes are set by fixing the
MODE1 and MODE0 package pins according to the
following table.
MODE1
VEE
VEE
MODE0
N.C.
VEE
Demultiplexing Mode
1:32
ALL 1’s OUTPUTS
For all modes the first high speed input bit in time
appears on RQ11, which is the most significant bit.
Subsequent input data is output sequentially to RQ12-
RQ48. Byte #1, RQ11-RQ18, is the most significant
byte. Odd or even parity selection is programmable by
PARSEL. If PARSEL is left open
(N.C.) the parity is
even. If PARSEL is tied to VEE the parity is odd.
In a 1:32 demultiplexing application, the TQ8223
regenerates the serial 2.48832 Gb/s data stream and
re-times it with the negative edge of the active 2.48832
GHz clock. The re-timed serial data stream is then 1:32
demultiplexed by the DEMUX block into an 32-bit wide
77.76 MHz data bus at RQ11-RQ48. A parity bit is
generated for each byte, and transmitted in parallel to
the data at RQPAR(1:4). The 32-bit wide data plus four
parity bits are then clocked out on the falling edge of
the internally generated 77.76 MHz clock. See Figure 6.
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