參數(shù)資料
型號(hào)： TRCV0110G
英文描述： ATM/SONET DEMULTIPLEXER|BIPOLAR|BGA|177PIN|PLASTIC
中文描述： 的ATM / SONET的分路器|雙極|的BGA | 177PIN |塑料
文件頁(yè)數(shù)： 15/26頁(yè)
文件大小： 476K
代理商： TRCV0110G
Agere Systems Inc.
15
Data Sheet
March 28, 2002
Clock Recovery, 1:16 Data Demultiplexer
TRCV0110G 10 Gbits/s Limiting Amplifier
Demultiplexer Operation
The serial 10 Gbits/s data is clocked into a 1:16 demultiplexer by the recovered 10 GHz clock. The demultiplexed
parallel data is retimed with a 622 MHz clock that is derived from the recovered clock. The relationship between
the serial input data and the parallel D[15:0] bits is given in Figure 8. D15 is the bit that was received first in time in
the serial input data stream.
0367.a(F)
Figure 8. DeMUX Clock to Output Data Relationship
Demultiplexer Data Mute (MUTEDMXN)
Setting the MUTEDMXN = 0 mutes the data going into the demultiplexer and forces all zeros to appear at the par-
allel outputs D[15:0].
CK622P/N Output Mute (MUTE622N)
The 622 MHz clock output CK622P/N can be forced to logic low by setting MUTE622N, which is an active-low
CMOS input with a pull-up resistor. A ground or logic low applied to MUTE622N mutes the CK622P/N output.
CKOP/N Output Frequency Select (FREQCKO)
Either a 155 MHz or 622 MHz clock output can be selected on the CKOP/N pins. A ground or logic low applied to
FREQCKO selects a 155 MHz clock to appear on the CKO output. A logic high or no connection selects a 622
MHz clock to appear on the CKO output.
CKOP/N Output Mute (MUTECKON)
The clock output CKOP/N can be forced to logic low by setting MUTECKON, which is an active-low CMOS input
with a pull-up resistor. A ground or logic low applied to MUTECKPN mutes the CKOP/N output.
Reset (RESETN)
The RESETN signal must be held active low for a minimum of 500 ns when the internal VCO is active and running,
in order for the internal logic to be completely reset.
CK622P/N
D[15:0]P/N
DATA 1
tDD1
tDD2
tPERIOD
DATA 3
DATA 2
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