參數(shù)資料
型號: TRCV0110G
英文描述: ATM/SONET DEMULTIPLEXER|BIPOLAR|BGA|177PIN|PLASTIC
中文描述: 的ATM / SONET的分路器|雙極|的BGA | 177PIN |塑料
文件頁數(shù): 19/26頁
文件大小: 476K
代理商: TRCV0110G
Agere Systems Inc.
19
Data Sheet
March 28, 2002
Clock Recovery, 1:16 Data Demultiplexer
TRCV0110G 10 Gbits/s Limiting Amplifier
Timing Characteristics
Note that all timing diagrams involving differential signals represent the positive signal as a solid line and the neg-
ative signal as a dashed line. This is especially important when referencing the rising or falling edge of a differential
signal.
Output Timing
The timing relationships between the output 622 MHz clock CK622P/N and the output demultiplexer data
D[15:0]P/N are shown in Figure 9.
0367.a(F)
Figure 9. DeMUX Transmit Timing with CK622
Table 14. LVDS Output Pin ac Timing Characteristics
Applicable
Pins
Symbol
Parameter
Conditions
*
* All signals differential, Z
LOAD
= 100
± 1%.
As defined by the
IEEE
standard 1596.3-1996.
Min
Typ
Max
Unit
CKOP/N
t
DC
Duty Cycle
Period
Period
Clock V
OD
(20%—80%)
Clock V
OD
(20%—80%)
Single Ended Output Amplitude
Duty Cycle
Period
Clock V
OD
(20%—80%)
Clock V
OD
(20%—80%)
Single Ended Output Amplitude
Time Delay from Clock Edge to
Data Edge
40
100
100
200
40
100
100
200
0.5
50
6.4
1.6
50
1.6
0.7
60
300
300
500
60
300
300
500
0.9
%
ns
ns
ps
ps
mV
%
ns
ps
ps
mV
ns
t
PERIOD0
t
PERIOD1
t
RISEC1
t
FALLC1
V
AMP
t
DC
t
PERIOD2
t
RISEC2
t
FALLC2
V
AMP
t
DD1
FREQCKO = 0
FREQCKO = 1
Rising clock edge
leads data
Rising clock edge lags
data
Measured differentially
CK622P/N
D[15:0]P/N
t
DD2
0.7
0.9
1.1
ns
t
RISED
t
FALLD
t
SKEW1
t
SKEW2
V
AMP
Data V
OD
(20%—80%)
Data V
OD
(20%—80%)
Differential Skew
Channel to Channel
Single Ended Output Amplitude
200
200
200
450
450
70
150
500
ps
ps
ps
ps
mV
CK622P/N
D[15:0]P/N
DATA 1
tDD1
tDD2
tPERIOD
DATA 3
DATA 2
相關(guān)PDF資料
PDF描述
TRF-70 Fuse
TRF-80 Fuse
TRF-100 Fuse
TRF-125 Fuse
TRF-160 Fuse
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TRCV012G5 制造商:AGERE 制造商全稱:AGERE 功能描述:TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
TRCV012G53XE1 制造商:AGERE 制造商全稱:AGERE 功能描述:TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
TRCV012G7 制造商:AGERE 制造商全稱:AGERE 功能描述:TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
TRCV012G73XE1 制造商:AGERE 制造商全稱:AGERE 功能描述:TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
TRD10-103 制造商:RCD 制造商全稱:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM