- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄272328 > TS(X)PC603EMAB/C4LN 32-BIT, 120 MHz, RISC PROCESSOR, CQFP240 PDF資料下載
參數(shù)資料
| 型號： | TS(X)PC603EMAB/C4LN |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 120 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CERAMIC, QFP-240 |
| 文件頁數(shù)： | 18/38頁 |
| 文件大小： | 632K |
| 代理商： | TS(X)PC603EMAB/C4LN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
TSPC603E
25/38
5.1.7.1. User-Level SPRs
The following 603e SPRs are accessible by user-level software :
D Link register (LR) - The link register can be used to provide the branch target address and to hold the return address after branch
and link instructions. The LR is 32 bits wide in 32-bit implementations.
D Count register (CTR) - The CRT is decremented and tested automatically as a result of branch-and-count instructions. The CTR
is 32 bits wide in 32-bit implementations.
D Integer exception register (XER) - The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit, and a field
specifying the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store String Word Indexed (stswx)
instruction.
5.1.7.2. Supervisor-Level SPRs
The 603e also contains SPRs that can be accessed only by supervisor-level software. These registers consist of the following :
D The 32-bit DSISR defines the cause of data access and alignment exceptions.
D The data address register (DAR) is a 32-bit register that holds the address of an access after an alignment or DSI exception.
D Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception
after a programmable delay.
D The 32-bit SDR1 specifies the page table format used in virtual-to-physical address translation for pages. (Note that physical
address is referred to as real address in the architecture specification).
D The machine status save/restore register 0 (SRR0) is a 32-bit register that is used by the 603e for saving the address of the instruc-
tion that caused the exception, and the address to return to when a Return from Interrupt (rfi) instruction is executed.
D The machine status save/restore register 1 (SRR1) is a 32-bit register used to save machine status on exceptions and to restore
machine status when an rfi instruction is executed.
D The 32-bit SPRG0-SPRG3 registers are provided for operating system use.
D The external access register (EAR) is a 32-bit register that controls access to the external control facility through the External
Control In Word Indexed (eciwx) and External Control Out Word Indexed (ecowx) instructions.
D The time base register (TB) is a 64-bit register that maintains the time of day and operates interval timers. The TB consists of two
32-bit fields - time base upper (TBU) and time base lower (TBL).
D The processor version register (PVR) is a 32-bit, read-only register that identifies the version (model) and revision level of the
PowerPC processor.
D Block address translation (BAT) arrays - The PowerPC architecture defines 16 BAT registers, divided into four pairs of data BATs
(DBATs) and four pairs of instruction BATs (IBATs). See Figure 15 for a list of the SPR numbers for the BAT arrays.
The following supervisor-level SPRs are implementation-specific to the 603e :
D The DMISS and IMISS registers are read-only registers that are loaded automatically upon an instruction or data TLB miss.
D The HASH1 and HASH2 registers contain the physical addresses of the primary and secondary page table entry groups (PTEGs).
D The ICMP and DCMP registers contain a duplicate of the first word in the page table entry (PTE) for which the table search is
looking.
D The required physical address (RPA) register is loaded by the processor with the second word of the correct PTE during a page
table search.
D The hardware implementation (HID0 and HID1) registers provide the means for enabling the 603e”s checkstops and features,
and allows software to read the configuration of the PLL configuration signals.
D The instruction address breakpoint register (IABR) is loaded with an instruction address that is compared to instruction addresses
in the dispatch queue. When an address match occurs, an instruction address breakpoint exception is generated.
Figure 15 shows all the 603e registers available at the user and supervisor level. The number to the right of the SPRs indicate the
number that is used in the syntax of the instruction operands to access the register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TS(X)PC603EMAU3LL | 32-BIT, 100 MHz, RISC PROCESSOR, CQFP240 |
| TS(X)PC603EMG2LL | 32-BIT, 80 MHz, RISC PROCESSOR, CBGA255 |
| TS(X)PC603EMGB/C2LN | 32-BIT, 80 MHz, RISC PROCESSOR, CBGA255 |
| TS(X)PC603EMGU/T2LN | 32-BIT, 80 MHz, RISC PROCESSOR, CBGA255 |
| TS(X)PC603EMGU2ML | 32-BIT, 80 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSXPC860SRVZQU66D | 功能描述:IC MPU POWERQUICC 66MHZ 357PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| TSXPCX1031 | 制造商:Schneider Electric 功能描述:CABLE TO PC SERIAL PORT (SUB-D9) 制造商:Schneider Electric 功能描述:PROGRAMMABLE CABLE 制造商:Schneider Electric 功能描述:MULTI-FUNCTION COMMUNICATION CABLE 制造商:Schneider Electric 功能描述:PROGRAMMABLE CABLE; Accessory Type:Programmable Cable; For Use With:Schneider Non-Ethernet Based Twido PLCs ;RoHS Compliant: Yes 制造商:Schneider Electric 功能描述:Programme cable for twido-nano-micro PLC |
| TSXPLP01 | 制造商:Schneider Electric 功能描述:BATTERY FOR TSX 37 制造商:Schneider Electric 功能描述:BATTERY FOR TSX 37 ;ROHS COMPLIANT: YES 制造商:Schneider Electric 功能描述:TSXPLP01 PLC replacement battery |
| TSXPLP101 | 制造商:Schneider Electric 功能描述:BATTERY TSX 37 QTY.10, TSXPLP101 |
| TSXPRGLDR | 制造商:Schneider Electric 功能描述:PROGRAM LOADER FOR 07/37 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。