參數(shù)資料
型號(hào)： TS(X)PC603EMAB/C4LN
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 120 MHz, RISC PROCESSOR, CQFP240
封裝： CERAMIC, QFP-240
文件頁(yè)數(shù)： 8/38頁(yè)
文件大?。?/td> 632K
代理商： TS(X)PC603EMAB/C4LN
TSPC603E
16/38
D Sleep mode sequence :
- Set sleep bit (HID0[10] = 1).
- 603e asserts quiesce request (QREQ).
- System asserts quiesce acknowledge (QACK).
- 603e enters sleep mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SMI, or MCP interrupts.
- Assert hard reset or soft reset.
D PLL may be disabled and SYSCLK may be removed while in sleep mode.
D Return to full-power mode after PLL and SYSCLK disabled in sleep mode :
- Enable SYSCLK.
- Reconfigure PLL into desired processor clock mode.
- System logic waits for PLL startup and relock time (100
msec).
- System logic asserts one of the sleep recovery signals (for example, INT or SMI).
3.6.4. Power Management Software Considerations
Since the 603e is a dual issue processor with out -of-order execution capability, care must be taken in how the power management
mode is entered. Furthermore, nap and sleep modes require all outstanding bus operations to be completed before the power man-
agement mode is entered. Normally during system configuration time, one of the power management modes would be selected by
setting the appropriate HID0 mode bit. Later on, the power management mode is invoked by setting the MSR[POW] bit. To provide a
clean transition into and out of the power management mode, the stmsr[POW] should be preceded by a sync instruction and fol-
lowed by an isync instruction.
3.6.5. Power dissipation
Table 8 : Power dissipation
Vdd = 3.3
± 5 % V dc, GND = 0 V dc, 0°C ≤ Tc ≤ 125°C
CPU clock Frequency
80 MHz
100 MHz
120 MHz
133 MHz
Units
Full-On Mode (DPM Enabled)
Typical
2.1
3.2
3.9
4.2
W
Max
3.0
4.0
4.8
5.3
W
Doze Mode1
Typical
0.8
1.0
1.2
1.3
W
Nap Mode1
Typical
70
80
85
mW
Sleep Mode1
Typical
40
45
50
mW
Sleep Mode-PLL Disabled1
Typical
5.0
6.0
mW
Sleep Mode-PLL and SYSCLK Disabled1
Typical
3.0
mW
Note 1 : The values provided for this mode do not include pad driver power (OVDD)
or analog supply power (AVDD). Worst-case AVDD = 15 mW
Note :
To calculate the power consumption at low temperature (–55oC), use a 1.25 factor
Maximum power measurements are performed with a worst case instruction mix at VDD=3.465V
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