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參數(shù)資料
| 型號： | TS(X)PC603EVAB/T5LL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 133 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CERAMIC, QFP-240 |
| 文件頁數(shù)： | 22/38頁 |
| 文件大?。?/td> | 632K |
| 代理商： | TS(X)PC603EVAB/T5LL |
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TSPC603E
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D Modified - The cache line is modified with respect to system memory ; that is, data for this address is valid only in the cache and
not in system memory.
D Exclusive - This cache line holds valid data that is identical to the data at this address in system memory. No other cache has
this data.
D Invalid - This cache line does not hold valid data.
Cache coherency is enforced by on-chip bus snooping logic. Since the 603e’s data cache tags are single ported, a simultaneous load
or store and snoop access represent a resource contention. The snoop access is given first access to the tags. The load or store then
occurs on the clock following snoop.
Figure 16 : Data cache organization
5.4. Exception model
The following subsections describe the PowerPC exception model and the 603e implementation, respectively.
5.4.1. PowerPC exception model
The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external singles, errors, or
unusual conditions arising in the execution of instructions, and differ from the arithmetic exceptions defined by the IEEE for floating-
point operations. When exceptions occur, information about the state of the processor is saved to certain registers and the processor
begins execution at an address (exception vector) predetermined for each exception. Processing of exceptions occurs in supervisor
mode.
Although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by examin-
ing a register associated with the exception - for example, the DSISR and the FPSCR. Additionally, some exception conditions can be
explicitly enable or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order ; therefore, although a particular implementation
may recognize exception conditions out of order, they are presented strictly in order. When an instruction-caused exception is recog-
nized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute
state, are required to complete before the exception is taken. Any exceptions caused by those instructions are handled first. Likewise,
exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the instruction currently in
the completion state successfully completes execution or generates an exception, and the completed store queue is emptied.
Unless a catastrophic causes a system reset or machine check exception, only one exception is handled at a time. If, for example, a
single instruction encounters multiple exception conditions, those conditions are encountered sequentially. After the exception hand-
ler handles an exception, the instruction execution continues until the next exception condition is encountered. However, in many
cases there is no attempt to re-execute the instruction. This method of recognizing and handling exception conditions sequentially
guarantees that exceptions are recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the program state from being lost due to a
system reset and machine check exception or to an instruction-caused exception in the exception handler, and before enabling exter-
nal interrupts.
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