參數(shù)資料
型號(hào)： TS(X)PC603EVAB/T5LL
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 133 MHz, RISC PROCESSOR, CQFP240
封裝： CERAMIC, QFP-240
文件頁(yè)數(shù)： 7/38頁(yè)
文件大?。?/td> 632K
代理商： TS(X)PC603EVAB/T5LL
TSPC603E
15/38
3.6.3.1. Full-Power Mode with DPM Disabled
Full-power mode with DPM disabled power mode is selected when the DPM enable bit (bit 11) in HID0 is cleared.
- Default state following power-up and HRESET.
- All functional units are operating at full processor speed at all times.
3.6.3.2. Full-Power Mode with DPM Enabled
Full-power mode with DPM enabled (HID0[11] = 1) provides on-chip power management without affecting the functionality or perfor-
mance of the 603e.
- Required functional units are operating at full processor speed.
- Functional units are clocked only when needed.
- No software or hardware intervention required after mode is set.
- Software/hardware and performance transparent.
3.6.3.3. Doze Mode
Doze ode disables most functional units but maintains cache coherency by enabling the bus interface unit and snooping. A snoop hit
will cause the 603e to enable the data cache, copy the data back to memory, disable the cache, and fully return to the doze state.
D Most functional units disabled.
D Bus snooping and time base/decrementer still enabled.
D Dose mode sequence :
- Set doze bit (HID0[8) = 1).
- 603e enters doze mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SMI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
D Transition to full-power state takes no more than a few processor cycles.
D PLL running and locked to SYSCLK.
3.6.3.4. Nap Mode
The nap mode disables the 603e but still maintains the phase locked loop (PLL) and the time base/decrementer. The time base can
be used to restore the 603e to full-on state after a programmed amount of time. Because bus snooping is disabled for nap and sleep
mode, a hardware handshake using the quiesce request (QREQ) and quiesce acknowledge (QACK) signals are requires to maintain
data coherency. The 603e will assert the QREQ signal to indicate that it is ready to disable bus snooping. When the system has
ensured that snooping is no longer necessary, it will assert QACK and the 603e will enter the sleep or nap mode.
D Time base/decrementer still enabled.
D Most functional units disabled (including bus snooping).
D All nonessential input receivers disables.
D Nap mode sequence :
- Set nap bit (HID0[9] = 1).
- 603e asserts quiesce request (QREQ) signal.
- System asserts quiesce acknowledge (QACK) signal.
- 603e enters sleep mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SPI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
D Transition to full-power takes no more than a few processor cycles.
D PLL running and locked to SYSCLK.
3.6.3.5. Sleep Mode
Sleep mode consumes the least amount of power of the four modes since all functional units are disabled. To conserve the maximum
amount of power, the PLL may be disabled and the SYSCLK may be removed. Due to the fully static design of the 603e, internal
processor state is preserved when no internal clock is present. Because the time base and decrementer are disabled while the 603e
is in sleep mode, the 603e’s time base contents will have to be updated from an external time base following sleep mode if accurate
time-of-day maintenance is required. Before the 603e enters the sleep mode, the 603e will assert the QREQ signal to indicate that it is
ready to disable bus snooping. When the system has ensured that snooping is no longer necessary, it will assert QACK and the 603e
will enter the sleep mode.
D All functional units disabled (including bus snooping and time base).
D All nonessential input receivers disabled :
- Internal clock regenerators disabled.
- PLL still running (see below).
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