參數(shù)資料
型號(hào): TS68020DESC03XA
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT01; Number of Contacts:41; Connector Shell Size:20; Connecting Termination:Solder; Circular Shell Style:Cable Receptacle
中文描述: 32-BIT, 20 MHz, MICROPROCESSOR, CPGA114
封裝: CERAMIC, PGA-114
文件頁數(shù): 11/45頁
文件大?。?/td> 1256K
代理商: TS68020DESC03XA
11
TS68020
2115A–HIREL–07/02
Dynamic (Switching)
Characteristics
The limits and values given in this section apply over the full case temperature range -
55
°
C to +125
°
C and V
CC
in the range 4.5V to 5.5V V
IL
= 0.5V and V
IH
= 2.4V (See also
note 12 and 13). The INTERVAL numbers refer to the timing diagrams. See Figure 5,
Figure 9 and Figure 12.
Table 6.
Dynamic Electrical Characteristics
Symbol
Parameter
Interval
Number
68020-16
68020-20
68020-25
Unit
Notes
Min
Max
Min
Max
Min
Max
t
CPW
Clock Pulse Width
2 , 3
24
95
20
54
19
61
ns
t
CHAV
Clock High to Address/FC/Size/RMC
Valid
6
0
30
0
25
0
25
ns
t
CHEV
Clock High to ECS, OCS Asserted
6A
0
20
0
15
0
12
ns
t
CHAZX
Clock High to Address/Data/FC/RMC/
Size High Impedance
7
0
60
0
50
0
40
ns
(11)
t
CHAZn
Clock High to Address/FC/Size/RMC
Invalid
8
0
0
0
ns
t
CLSA
Clock Low to AS, DS Asserted
9
3
30
3
25
3
18
ns
t
STSA
AS to DS Assertion (Read)(Skew)
9A
-15
15
-10
10
-10
10
ns
(1)
t
ECSA
ECS Width Asserted
10
20
15
15
ns
t
OCSA
OCS Width Asserted
10A
20
15
15
ns
t
EOCSN
ECS, OCS Width Negated
10B
15
10
5
ns
(11)
t
AVSA
Address/FC/Size/RMC Valid to AS
Asserted (and DS Asserted, Read)
11
15
10
6
ns
(6)
t
CLSN
Clock Low to AS, DS Negated
12
0
30
0
25
0
15
ns
t
CLEN
Clock Low to ECS/OCS Negated
12A
0
30
0
25
0
15
ns
t
SNAI
AS, DS Negated to Address/FC/
Size/RMC Invalid
13
15
10
10
ns
t
SWA
AS (and DS, Read) Width Asserted
14
100
85
70
ns
t
SWAW
DS Width Asserted, Write
14A
40
38
30
ns
t
SN
AS, DS Width Negated
15
40
38
30
ns
(11)
t
SNSA
DS Negated to AS Asserted
15A
35
30
25
ns
(8)
t
CSZ
Clock High to AS/DS/R/W/DBEN High
Impedance
16
60
50
40
ns
(11)
t
SNRN
AS, DS Negated to R/W High
17
15
10
10
ns
(6)
t
CHRH
Clock High to R/W High
18
0
30
0
25
0
20
ns
t
CHRL
Clock High to R/W Low
20
0
30
0
25
0
20
ns
t
RAAA
R/W High to AS Asserted
21
15
10
5
ns
(6)
t
RASA
R/W Low to DS Asserted (Write)
22
75
60
50
ns
(6)
t
CHDO
Clock High to Data Out Valid
23
30
25
25
ns
t
SNDI
AS, DS Negated to Data Out Valid
25
15
10
5
ns
(6)
t
DNDBN
DS Negated to DBEN Negated (Write)
25A
15
10
5
ns
(9)
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