參數(shù)資料
型號： TS68020DESC03XA
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT01; Number of Contacts:41; Connector Shell Size:20; Connecting Termination:Solder; Circular Shell Style:Cable Receptacle
中文描述： 32-BIT, 20 MHz, MICROPROCESSOR, CPGA114
封裝： CERAMIC, PGA-114
文件頁數(shù)： 13/45頁
文件大?。?/td> 1256K
代理商： TS68020DESC03XA
13
TS68020
2115A–HIREL–07/02
Notes:
1. This number can be reduced to 5 nanoseconds if the strobes have equal loads.
2. If the asynchronous setup time (= 47) requirements are satisfied, the DSACKx low to data setup time (= 31) and DSACKx
low to BERR low setup time (= 48) can be ignored. The data must only satisfy the data in to clock low setup time (= 27) for
the following clock cycle, BERR must only satisfy the late BERR low to clock setup time (= 27) for the following clock cycle.
3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or DSACK1 to DSACK0
asserted pattern = 47 must be met by DSACK0 and DSACK1.
4. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous input setup time (= 47).
5. DBEN may stay asserted on consecutive write cycles.
6. Actual value depends on the clock input waveform.
7. This pattern indicates the minimum high time for ECS and OCS in the event of an internal cache hit followed immediately by
a cache miss or operand cycle.
8. This specification guarantees operations with the 68881 co-processor, and defines a minimum time for DS negated to AS
asserted (= 13A). Without this parameter, incorrect interpretation of = 9A and = 15 would indicate that the 68020 does not
meet 68881 requirements.
9. This pattern allows the systems designer to guarantee data hold times on the output side of data buffers that have output
enable signals generated with DBEN.
10. Guarantees that an alternate bus master has stopped driving the bus when the 68020 regains control of the bus after an
arbitration sequence.
11. Cannot be tested. Provided for system design purposes only.
12. T
case
= -55
°
C and +130
°
C in a Power off condition under Thermal soak for 4 minutes or until thermal equilibrium. Electrical
parameters are tested “instant on” 100 m sec. after power is applied.
13. All outputs unload except for load capacitance. Clock = fmax,
LOW: HALT, RESET
HIGH: DSACK0, DSACK1, CDIS, IPL0-IPL2, DBEN, AVEC, BERR.
f
Frequency of Operation
8.0
16.67
12.5
20.0
12.5
25
MHz
t
RADC
R/W Asserted to Data Bus Impedance
Change
55
30
25
20
(11)
t
HRPW
RESET Pulse Width (Reset Instruction)
56
512
512
512
Clks
(11)
t
BNHN
BERR Negated to HALT Negated
(Rerun)
57
0
0
0
ns
(11)
t
GANBD
BGACK Negated to Bus Driven
58
1
1
1
Clks
(10)(11)
t
GNBD
BG Negated to Bus Driven
59
1
1
1
Clks
(10)(11)
Table 6.
Dynamic Electrical Characteristics (Continued)
Symbol
Parameter
Interval
Number
68020-16
68020-20
68020-25
Unit
Notes
Min
Max
Min
Max
Min
Max
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TS68020DESC03XC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:HCMOS 32-bit Virtual Memory Microprocessor
TS68020DESC03YA 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:HCMOS 32-bit Virtual Memory Microprocessor
TS68020DESC03YC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:HCMOS 32-bit Virtual Memory Microprocessor
TS68020DESC04XA 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:HCMOS 32-bit Virtual Memory Microprocessor
TS68020DESC04XC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:HCMOS 32-bit Virtual Memory Microprocessor
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