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參數(shù)資料
| 型號： | TS68040DESC01XAA |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Third- Generation 32-bit Microprocessor |
| 中文描述： | 32-BIT, 25 MHz, MICROPROCESSOR, CPGA179 |
| 封裝： | CERAMIC, PGA-179 |
| 文件頁數(shù)： | 21/49頁 |
| 文件大?。?/td> | 1637K |
| 代理商： | TS68040DESC01XAA |
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21
TS68040
2116A–HIREL–09/02
Notes:
1. Output timing is specified for a valid signal measured at the pin. Large buffer timing is specified driving a 50
transmission
line with a length characterized by a 2.5 ns one-way propagation delay, terminated through 50
to 2.5V. Large buffer output
impedance is typically 3
, resulting in incident wave switching for this environment. Small buffer timing is specified driving
an unterminated 30
transmission line with a length characterized by a 2.5 ns one-way propagation delay. Small buffer out-
put impedance is typically 30
; the small buffer specifications include approximately 5 ns for the signal to propagate the
length of the transmission line and back.
2. All testing to be performed using worst-case test conditions unless otherwise specified.
3. The following pins are active low: AVEC, BG, BS, BR, CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, MDIS, MI,
RST0, RSTI, TA, TBI, TCI, TEA, TIP, TRST, TS and W of R/W.
4. Maximum operating junction temperature (T
J
) = +125°. Minimum case operating temperature (T
C
) = -55°. This device is not
tested at T
C
= +125°. Testing is performed by setting the junction temperature T
J
= +125°and allowing the case and ambient
temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.
5. Timing specifications 11, 20 and 38 for address bus output timing apply when normal bus operation is selected. Specifica-
tions 26, 27 and 28 should be used when the multiplexed bus mode of operation is enabled.
6. Timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected. Specifications 28
and 29 should be used when the multiplexed bus mode of operation is enabled.
Table 15.
Input AC Timing Specifications (Figure 9 to Figure 15)
-55°C
≤
T
C
≤
T
Jmax
; 4.75V
≤
V
CC
≤
5.25V unless otherwise specified
(1)(2)(3)(4)
Num
Characteristic
25 MHz
33 MHz
Unit
Min.
Max.
Min.
Max.
15
Data-in Valid to BCLK (Setup)
5
4
ns
16
BCLK to Data-in Invalid (Hold)
4
4
ns
17
BCLK to Data-in High Impedance (Read Followed By Write)
49
36.5
ns
22a
TA Valid to BCLK (Setup)
10
10
ns
22b
TEA Valid to BCLK (Setup)
10
10
ns
22c
TCI Valid to BCLK (Setup)
10
10
ns
22d
TBI Valid to BCLK (Setup)
11
10
ns
23
BCLK to TA, TEA, TCI, TBI Invalid (Hold)
2
2
ns
24
AVEC Valid to BCLK (Setup)
5
5
ns
25
BCLK to AVEC Invalid (Hold)
2
2
ns
31
DLE Width High
8
8
ns
32
Data-in Valid to DLE (Setup)
2
2
ns
33
DLE to Data-in Invalid (Hold)
8
8
ns
34
BCLK to DLE Hold
3
3
ns
35
DLE High to BCLK
16
12
ns
36
Data-in Valid to BCLK (DLE Mode Setup)
5
5
ns
37
BCLK Data-in Invalid (DLE Mode Hold)
4
4
ns
41a
BB Valid to BCLK (Setup)
7
7
ns
41b
BG Valid to BCLK (Setup)
8
7
ns
41c
CDIS, MDIS Valid to BCLK (Setup)
10
8
ns
41d
IPLn Valid to BCLK (Setup)
4
3
ns
42
BCLK to BB, BG, CDIS, IPLn, MDIS Invalid (Hold)
2
2
ns
44a
Address Valid to BCLK (Setup)
8
7
ns
44b
SIZn Valid BCLK (Setup)
12
8
ns
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| TS68040DESC01ZAA | Third- Generation 32-bit Microprocessor |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TS68040DESC01XCA | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Third- Generation 32-bit Microprocessor |
| TS68040DESC01YCA | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Third- Generation 32-bit Microprocessor |
| TS68040DESC01ZAA | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Third- Generation 32-bit Microprocessor |
| TS68040DESC01ZCA | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Third- Generation 32-bit Microprocessor |
| TS68040DESC02XAA | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Third- Generation 32-bit Microprocessor |
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