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參數(shù)資料
| 型號： | TS68040MR25A |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Third- Generation 32-bit Microprocessor |
| 中文描述： | 32-BIT, 25 MHz, MICROPROCESSOR, CPGA179 |
| 封裝： | CERAMIC, PGA-179 |
| 文件頁數(shù)： | 1/49頁 |
| 文件大?。?/td> | 1637K |
| 代理商： | TS68040MR25A |
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1
Features
26-42 MIPS Integer Performance
3.5-5.6 MFLOPS Floating-Point-Performance
IEEE 754-Compatible FPU
Independent Instruction and Data MMUs
4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed
Simultaneously
32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
User-Object-Code Compatibility with All Earlier TS68000 Microprocessors
Multimaster/Multiprocessor Support via Bus Snooping
Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize
Throughput
4G bytes Direct Addressing Range
Software Support Including Optimizing C Compiler and UNIX
System V Port
IEEE P 1149-1 Test Mode (JTAG)
f = 25 MHz, 33 MHz; V
CC
= 5V ± 5%; P
D
= 7W
The Use of the TS88915T Clock Driver is Suggested
Description
The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-
bit microprocessors. The TS68040 is a virtual memory microprocessor employing
multiple, concurrent execution units and a highly integrated architecture to provide
very high performance in a monolithic HCMOS device. On a single chip, the TS68040
integrates a 68030-compatible integer unit, an IEEE 754-compatible floating-point unit
(FPU), and fully independent instruction and data demand-paged memory manage-
ment units (MMUs), including 4K bytes independent instruction and data caches. A
high degree of instruction execution parallelism is achieved through the use of multi-
ple independent execution pipelines, multiple internal buses, and a full internal
Harvard architecture, including separate physical caches for both instruction and data
accesses. The TS68040 also directly supports cache coherency in multimaster appli-
cations with dedicated on-chip bus snooping logic.
The TS68040 is user-object-code compatible with previous members of the TS68000
Family and is specifically optimized to reduce the execution time of compiler-gener-
ated code. The 68040 HCMOS technology, provides an ideal balance between speed,
power, and physical device size.
Figure 1 is a simplified block diagram of the TS68040. Instruction execution is pipe-
lined in both the integer unit and FPU. Independent data and instruction MMUs control
the main caches and the address translation caches (ATCs). The ATCs speed up log-
ical-to-physical address translations by storing recently used translations. The bus
snooper circuit ensures cache coherency in multimaster and multiprocessing
applications.
Screening
MIL-STD-883
DESC. Drawing 5962-93143
Atmel Standards
Third-
Generation
32-bit
Microprocessor
TS68040
Rev. 2116A–HIREL–09/02
相關PDF資料 |
PDF描述 |
|---|---|
| TS68040VF25A | Third- Generation 32-bit Microprocessor |
| TS68230CFN10 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230FN | HMOS PARALLEL INTERFACE/TIMER |
| TS68230 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP10 | HMOS PARALLEL INTERFACE/TIMER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TS68040MR33A | 制造商:e2v technologies 功能描述:MPU TS68000 32BIT HCMOS 33MHZ 179PIN PGA - Trays |
| TS68040MRB/C25A | 制造商:e2v Aerospace & Defense 功能描述:MPU TS68000 32-Bit HCMOS 25MHz 179-Pin PGA 制造商:e2v technologies 功能描述:TS68040MRB/C25A - Rail/Tube 制造商:e2v technologies 功能描述:5962-9314301MXC - Rail/Tube |
| TS68040MRB/C33A | 制造商:e2v technologies 功能描述:TS68040MRB/C33A - Rail/Tube |
| TS68040MRD/T25A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Third- Generation 32-bit Microprocessor |
| TS68040MRD/T33A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Third- Generation 32-bit Microprocessor |
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