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參數(shù)資料
| 型號： | TS68040VF25A |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Third- Generation 32-bit Microprocessor |
| 中文描述： | 32-BIT, 25 MHz, MICROPROCESSOR, CQFP196 |
| 封裝： | CAVITY UP, CERAMIC, QFP-196 |
| 文件頁數(shù)： | 10/49頁 |
| 文件大?。?/td> | 1637K |
| 代理商： | TS68040VF25A |
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10
TS68040
2116A–HIREL–09/02
Thermal Considerations
General Thermal
Considerations
This section is only given as user information.
As microprocessors are becoming more complex and requiring more power, the need to
efficiently cool the device becomes increasingly more important. In the past, the
TS68000 Family, has been able to provide a 0-70°C ambient temperature part for
speeds less than 40 MHz. However, the TS68040, which has a 50 MHz arithmetic logic
unit (ALU) speed, is specified with a maximum power dissipation for a particular mode, a
maximum junction temperature, and a thermal resistance from the die junction to the
case. This provides a more accurate method of evaluating the environment, taking into
consideration both the air-flow and ambient temperature available. This also allows a
user the information to design a cooling method which meets both thermal performance
requirements and constraints of the board environment.
This section discusses the device characteristics for thermal management, several
methods of thermal management, and an example of one method of cooling the
TS68040.
Thermal Device
Characteristics
The TS68040 presents some inherent characteristics which should be considered when
evaluating a method of cooling the device. The following paragraphs discuss these
die/package and power considerations.
Die and Package
The TS68040 is being placed in a cavity-down alumina-ceramic 179-pin PGA that has a
specified thermal resistance from junction to case of 1°C/W. This package differs from
previous TS68000 Family PGA packages which were cavity up. This cavity-down design
allows the die to be attached to the top surface of the package, which increases the abil-
ity of the part to dissipate heat through the package surface or an attached heat sink.
The maximum perimeter that the TS68040 allows for a heat sink on its surface without
interfering with the capacitor pads is 1.48" x 1.48". The specific dimensions and design
of the particular heat sink will need to be determined by the system designer considering
both thermal performance requirements and size requirements.
Power Considerations
The TS68040 has a maximum power rating, which varies depending on the operating
frequency and the output buffer mode combination being used. The large buffer output
mode dissipates more power than the small, and the higher frequencies of operation
dissipate more power than the lower frequencies. The following paragraphs discuss
trade-offs in using the different output buffer modes, calculation of specific maximum
power dissipation for different modes, and the relationship of thermal resistances and
temperatures.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TS68230CFN10 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230FN | HMOS PARALLEL INTERFACE/TIMER |
| TS68230 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP10 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP8 | HMOS PARALLEL INTERFACE/TIMER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS68040VF33A | 制造商:e2v technologies 功能描述:MPU TS68000 32BIT HCMOS 33MHZ 196CQFP - Trays |
| TS68040VFT25A | 制造商:e2v technologies 功能描述:TS68040VFT25A - Trays |
| TS68040VFT33A | 制造商:e2v technologies 功能描述:MPU TS68000 32BIT HCMOS 33MHZ 196PIN TIE BARE CQFP - Trays |
| TS68040VR1-25A | 制造商:e2v technologies 功能描述:MPU TS68000 32BIT HCMOS 25MHZ 179PIN PGA - Trays |
| TS68040VR1-33A | 制造商:e2v technologies 功能描述:TS68040VR1-33A - Trays |
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