參數(shù)資料
型號(hào): TS68302VA16
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Integrated Multiprotocol Processor IMP
中文描述: 16-BIT, 16.67 MHz, RISC MICROCONTROLLER, CQFP132
封裝: CERAMIC, QFP-132
文件頁數(shù): 30/47頁
文件大小: 1149K
代理商: TS68302VA16
30
TS68302
2117A–HIREL–11/02
Notes:
1. The ratio CLK/L1CLK must be greater than 2.5/1.
2. Schmitt trigger used on input buffer.
3. Condition C
L
= 150 pF. L1T x D becomes valid after the L1CLK rising edge or L1SY1, whichever is later.
4. SDS1-SDS2 become valid after the L1CLK rising edge or L1SY1, whichever is later.
5. See Figure 24.
Table 20.
AC Electrical Specifications - GCI Timing
(5)
f = 16.67 MHz
GCI supports the NORMAL mode and the GCI channel 0 (GCN0) in MUX mode. Normal mode uses 512 kHz clock rate
(256K bit rate). MUX mode uses 256 x n - 3068K bits/sec (clock rate is data rate x 2). The ratio CLK/L1CLK must be greater
than 2.5/1.
Num.
Parameter
Min
Max
Unit
L1CLK GCI clock frequency (normal mode)
(1)
512
kHz
280
L1CLK clock period normal mode
(1)
1800
2100
ns
281
L1CLK width low/high normal mode
840
1450
ns
282
L1CLK rise/fall time normal mode
(2)
-
-
ns
L1CLK (GCI clock) period (MUX mode)
(1)
6.668
MHz
280
L1CLK clock period MUX mode
(1)
150
ns
281
L1CLK width low/high MUX mode
55
ns
282
L1CLK rise/fall time MUX mode
(2)
-
-
ns
283
L1SY1 sync setup time to L1CLK falling edge
30
ns
284
L1SY1 sync hold time from L1CLK falling edge
50
ns
285
L1T x D active delay (from L1CLK rising edge)
(3)
0
100
ns
286
L1T x D active delay (from L1SY1 rising edge)
(3)
0
100
ns
287
L1R x D setup time to L1CLK rising edge
20
ns
288
L1R x D hold time from L1CLK rising edge
50
ns
289
Time between successive L1SY1 in normal mode
SCIT mode
64
192
L1CLK
L1CLK
290
SDS1-SDS2 active delay from L1CLK riding edge
(4)
10
90
ns
291
SDS1-SDS2 active delay from L1SY1 rising edge
(4)
10
90
ns
292
SDS1-SDS2 inactive delay from L1CLK falling edge
10
90
ns
293
GCIDCL (GCI Data clock) active delay
0
50
ns
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