參數(shù)資料
型號(hào)： TS68302VA16
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Integrated Multiprotocol Processor IMP
中文描述： 16-BIT, 16.67 MHz, RISC MICROCONTROLLER, CQFP132
封裝： CERAMIC, QFP-132
文件頁(yè)數(shù)： 36/47頁(yè)
文件大小： 1149K
代理商： TS68302VA16
36
TS68302
2117A–HIREL–11/02
Figure 28.
Interrupt Controller Block Diagram
The interrupt controller also receives external (EXRQ) requests. EXRQ interrupts are
received by the IMP according to the operational mode selected. In the normal opera-
tional mode, EXRQ interrupts are encoded onto the IPL lines. In the dedicated
operational mode, EXRQ interrupts are presented directly as IRQ7, IRQ6, and IRQ1.
The interrupt controller block diagram is shown in Figure 28. The interrupt controller fea-
tures are as follows:
two operational modes: normal and dedicated,
eighteen priority-organized interrupt sources (internal and external),
fully nested interrupt environment,
unique vector number for each internal/external source,
three selectable interrupt request/interrupt acknowledge pairs.
Parallel I/O Ports
Port A and port B are two general-purpose I/O ports. Each pin in the 16-bit port A may
be configured as a general-purpose I/O pin or as a dedicated peripheral interface pin.
Port B has 12 pins. Eight pins may be configured as general-purpose pins or as dedi-
cated peripheral interface pins, and four are general-purpose pins, each with interrupt
capability.
SCC1 EVENT
REGISTER
SCC2 EVENT
REGISTER
SCC3 EVENT
REGISTER
SCC1 MASK
REGISTER
SCC2 MASK
REGISTER
SCC3 MASK
REGISTER
I
I
I
1
1
1
TS68000 CORE
DATA BUS
IRQ7/
IPL0
IRQ6/
IPL1
IRQ1/
IPL2
INTERRUPT
PRIORITY
RESOLVER
IPL2-IPL0 TO
TS68000 CORE
IACK6
IACK1
IACK7
VECTOR
GENERATION
LOGIC
TIMERS
SCP
SMCs
DMA
PB8-PB11
3
1
2
2
4
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