參數(shù)資料
型號(hào)： TS68332DESC01ZC
廠商： ATMEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： High performance 32-bit integrated microcontroller
中文描述： 32-BIT, 16.78 MHz, MICROCONTROLLER, CPGA132
封裝： CERAMIC, PGA-132
文件頁(yè)數(shù)： 13/56頁(yè)
文件大?。?/td> 1510K
代理商： TS68332DESC01ZC
13
TS68332
2118A–HIREL–03/02
7. TheRAMmodulewillnotswitchintostandbymodeaslongasV
SB
doesnotexceedV
DD
bymorethan0.5-volt.
TheRAMarraycannotbeaccessedwhilethemoduleisinstandbymode.
8. WhenV
DD
istransitioningduringpower-uporpower-downsequence,andV
SB
isapplied,currentflowsbetweentheV
STBY
andV
DD
pins,whichcausesstandbycurrenttoincreasetowardthemaximumtransientconditionspecification.Systemnoise
ontheV
DD
andV
STBY
pinscancontributetothiscondition.
9. Powerdissipationmeasuredatspecifiedsystemclockfrequency,allmodulesactive.Powerdissipationcanbecalculated
usingtheexpression:
P
D
=MaximumV
DD
(I
DD
+I
DDSYN
+I
SB
)
I
DD
includessupplycurrentsforalldevicemodulespoweredbyV
DDE
andV
DDI
pins.
10. Thisparameterisperiodicallysampledratherthan100%tested.
Dynamic(Switching)
Characteristics
TheINTERVALnumbersrefertothetimingdiagram.
Sp
Notes:
1. Allinternalregistersretaindataat0Hz.
2. Thisparameterisperiodicallysampledratherthan100%tested.
3. Assumesthatalow-leakageexternalfilternetworkisusedtoconditionclocksynthesizerinputvoltage.Totalexternalresis-
tancefromXFCpinduetoexternalleakagemustbegreaterthan15M
toguaranteethisspecification.Filternetwork
geometrycanvarydependinguponoperatingenvironment.
4. Properlayoutproceduresmustbefollowedtoachievespecifications.
5. AssumesthatstableV
DDSYN
isapplied,andthatthecrystaloscillatorisstable.LocktimeismeasuredfromthetimeV
DD
and
V
DDSYN
arevaliduntilRESETisreleased.ThisspecificationalsoappliestotheperiodrequiredforPLLlockafterchanging
theWandYfrequencycontrolbitsinthesynthesizercontrolregister(SYNCR)whilethePLLisrunning,andtotheperiod
requiredfortheclocktolockafterLPSTOP.
6. InternalVCOfrequency(f
VCO
)isdeterminedbySYNCRWandYbitvalues.TheSYNCRXbitcontrolsadivide-by-twocir-
cuitthatisnotinthesynthesizerfeedbackloop.WhenX=0,thedividerisenabled,andf
sys
=f
VCO
:4.WhenX=1,the
dividerisdisabled,andf
sys
=f
VCO
:2.Xmustequalonewhenoperatingatmaximumspecifiedf
sys
.
7. Stabilityistheaveragedeviationfromtheprogrammedfrequencymeasuredoverthespecifiedintervalatmaximumf
sys
.
Measurementsaremadewiththedevicepoweredbyfilteredsuppliesandclockedbyastableexternalclocksignal.Noise
injectedintothePLLcircuitryviaV
DDSYN
andV
SS
andvariationincrystaloscillatorfrequencyincreasetheCstabpercentage
foragiveninterval.Whenclockstabilityisacriticalconstraintoncontrolsystemoperation,thisparametershouldbemea-
suredduringfunctionaltestingofthefinalsystem.
Table5.
ClockControlTiming.V
DD
andV
DDSYN
=5.0V
DC
±10%for16.78MHzand5.0V
DC
±5%for20.97MHz;
V
SS
=0V
DC
;T
C
=-55°Cto+125°Cor-40°Cto+85°C
Number
Symbol
Parameter
16.78
20.97
Unit
Min
Max
Min
Max
1
f
ref
PLLreferencefrequencyrange
25
50
25
50
kHz
2
f
sys
Systemfrequency
(1)
On-chipPLLsystemfrequency
Externalclockoperation
dc
0.131
dc
16.78
16.78
16.78
dc
0.131
dc
20.97
20.97
20.97
MHz
MHz
MHz
3
f
lpll
PLLlocktime
(2)(3)(4)(5)
-
20
-
20
ms
4
f
vco
VCOfrequency
(6)
-
2(f
sys
max)
-
2(f
sys
max)
MHz
5
f
LIMP
Limpmodeclockfrequency
SYNCRXbit=0
SYNCRXbit=1
-
-
f
sys
max/2
f
sys
max
-
-
f
sys
max/2
f
sys
max
MHz
MHz
6
C
stab
CLKOUTstability
(2)(3)(4)(7)
Shortterm(5μsinterval)
Longterm(500μsinterval)
-05
-0.05
05
0.05
-05
-0.05
05
0.05
%
%
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