參數(shù)資料
型號(hào)： TS80C31X2-MIE
廠商： Atmel
文件頁(yè)數(shù)： 3/42頁(yè)
文件大小： 0K
描述： IC MCU 8BIT 40/20MHZ 44-VQFP
標(biāo)準(zhǔn)包裝： 9
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40/20MHz
連通性： UART/USART
外圍設(shè)備： POR
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類(lèi)型： ROMless
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-QFP
包裝： 托盤(pán)
11
4428E–8051–02/08
AT/TS80C31X2
9.
TS80C31X2 Serial I/O Port
The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.
It provides both synchronous and asynchronous communication modes. It operates as an Uni-
versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates
Serial I/O port includes the following enhancements:
Framing error detection
Automatic address recognition
9.1
Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1).
Figure 9-1.
Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
9-3.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 9-
Figure 9-2.
UART Timings in Mode 1
RI
TI
RB8
TB8
REN
SM2
SM1
SM0/FE
IDL
PD
GF0
GF1
POF
-
SMOD0
SMOD1
To UART framing error control
SM0 to UART mode control (SMOD = 0)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD
D7
D6
D5
D4
D3
D2
D1
D0
FE
SMOD0=1
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