參數(shù)資料
型號： TS80C51RD2-LIE
廠商： Atmel
文件頁數(shù)： 80/84頁
文件大小： 0K
描述： IC MCU 8BIT 768BYTE 30MHZ 44VQFP
標(biāo)準(zhǔn)包裝： 800
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 30/20MHz
連通性： UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器類型： ROMless
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-QFP
包裝： 托盤
2007-2012 Microchip Technology Inc.
DS70292G-page 83
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
6.4
Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
VDD crosses the VPOR threshold and the delay TPOR
has elapsed. The delay TPOR ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the
specified
starting
voltage
and
rise
rate
requirements to generate the POR. Refer to
The POR status bit (POR) in the Reset Control register
(RCON<0>) is set to indicate the Power-on Reset.
6.4.1
Brown-out Reset (BOR) and
Power-up timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the VDD is too low
(VDD < VBOR) for proper device operation. The BOR cir-
cuit keeps the device in Reset until VDD crosses VBOR
threshold and the delay TBOR has elapsed. The delay
TBOR ensures the voltage regulator output becomes
stable.
The BOR status bit (BOR) in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (TPWRT) is programmed by
the Power-on Reset Timer Value Select bits
(FPWRT<2:0>) in the POR Configuration register
(FPOR<2:0>), which provides eight settings (from 0 ms
for further details.
Figure 6-3 shows the typical brown-out scenarios. The
reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point
TABLE 6-2:
OSCILLATOR DELAY
Symbol
Parameter
Value
VPOR
POR threshold
1.8V nominal
TPOR
POR extension time
30
μs maximum
VBOR
BOR threshold
2.5V nominal
TBOR
BOR extension time
100
μs maximum
TPWRT
Programmable power-up time delay
0-128 ms nominal
TFSCM
Fail-Safe Clock Monitor Delay
900
μs maximum
Note:
When the device exits the Reset condi-
tion (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
all
operating
parameters
within
specification.
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