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參數(shù)資料
| 型號(hào)： | TS8308500CG |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | 1.27 MM PITCH, HEAT SINK, CERAMIC, BGA-72 |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 641K |
| 代理商： | TS8308500CG |
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TS8308500
Preliminary Specification
ββββ-site
Differential versus single ended analog input operation
The TS8308500 can operate at full speed in either differential or single ended configuration.
This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceding the Sample and hold stage), which
has been designed in order to be entered either in differential mode or single–ended mode.
This is true so long as the out of phase analog input pin VINB is 50 ohms terminated very closely to one of the neighboring shield ground pins
(52, 53, 58, 59) which constitute the local ground reference for the inphase analog input pin (VIN).
Thus the differential analog input preamplifier will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as
common mode effects.
In typical single–ended configuration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through the 50 ohms
termination resistor.
In single–ended input configuration, the in-phase input amplitude is 0.5 Volt peak to peak, centered on 0V. (or -2 dBm into 50 ohms.)
The inverted phase input is at ground potential through the 50 ohms termination resistor.
However, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential mode.
Typical Single ended analog input configuration
VIN or VINB
VIN or VINB double pads
50
(on packagel)
50
reverse termination
1M
3 pF
-250
250
[mV]
500 mV
Full Scale
analog input
t
VINB
VIN
VINB = 0V
VIN = +/- 250 mV
500 mV diff
7.4.
CLOCK INPUTS (CLK) (CLKB)
The TS8308500 can be clocked at full speed without noticeable performance degradation in either differential or single ended configuration.
This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed in order to be entered
either in differential or single–ended mode.
Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor spectral density, @ 1 KHz from carrier ,
assuming a single tone 4 dBm input for the clock signal.
7.4.1.
SINGLE ENDED CLOCK INPUT (GROUND COMMON MODE)
Although the clock inputs were intended to be driven differentially with nominal -0.8V / -1.8V ECL levels, the TS8308500 clock buffer can
manage a single–ended sinewave clock signal centered around 0 Volt. This is the most convenient clock input configuration as it does not
require the use of a power splitter.
No performance degradation ( e.g. : due to timing jitter) is observed in this particular single–ended configuration up to 500 MSPS Nyquist
conditions ( Fin = 250 MHz ).
This is all the more so true since the inverted phase clock input pin is 50 ohms terminated on the package (that is very close to one of the
neighboring shield ground pin, which constitutes the local Ground reference for the inphase clock input).
Thus the TS8308500 differential clock input buffer will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as
common mode effects.
Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance.
The typical inphase clock input amplitude is 1 Volt peak to peak, centered on 0 Volt (ground) common mode.
This corresponds to a typical clock input power level of 4 dBm into the 50 ohms termination resistor.
Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors.
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