參數(shù)資料
型號: TS8308500CG
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
封裝: 1.27 MM PITCH, HEAT SINK, CERAMIC, BGA-72
文件頁數(shù): 38/42頁
文件大小: 641K
代理商: TS8308500CG
5
Preliminary Specification
ββββ-site
TS8308500
3.3.
ELECTRICAL OPERATING CHARACTERISTICS
VEE = DVEE = -5 V ; VCC = +5 V ; VIN -VINB = 500 mVpp Full Scale differential input ;
Digital outputs 75 or 50
differentially terminated ;
Tj (typical) = 70
°C.
Parameter
Symb
Test
level
Min
Typ
Max
Unit
POWER REQUIREMENTS
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
VCC
VPLUSD
1
4
4.5
1.4
5
0
2.4
5.5
2.6
V
Positive supply current
Analog
Digital
ICC
IPLUSD
1
420
130
445
145
mA
Negative supply voltage
VEE
1
-5.5
-5
-4.5
V
Negative supply current
Analog
Digital
AIEE
DIEE
1
185
160
200
180
mA
Nominal power dissipation
PD
1
3.8
4.1
W
Power supply rejection ratio
(note 2)
PSRR
4
0.5
2
mV/V
RESOLUTION
8bits
ANALOG INPUTS
Full Scale Input Voltage range (differential mode)
( 0 Volt common mode voltage )
VIN
VINB
4
-125
125
mV
Full Scale Input Voltage range (single–ended input option )
(see Application
Notes)
VIN
VINB
4
-250
0
250
mV
Analog input capacitance
CIN
43
3.5
pF
Input bias current
IIN
410
20
A
Input Resistance
RIN
40.5
1
M
Full Power input Bandwidth
FPBW
4
1.2
1.3
GHz
Small Signal input Bandwidth (10 % full scale)
SSBW
4
1.2
1.3
GHz
CLOCK INPUTS
Logic compatibility for clock inputs
(note 10 )
(see Application Notes)
ECL or specified clock input
power level in dBm
ECL Clock inputs voltages (VCLK or VCLKB) :
4
Logic “0” voltage
VIL
-1.5
V
Logic “1” voltage
VIH
-1.1
V
Logic “0” current
IIL
550
A
Logic “1” current
IIH
550
A
Clock input power level into 50
termination
DBm into 50
Clock input power level
4
-2
4
10
dBm
Clock input capacitance
CCLK
43
3.5
pF
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