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參數(shù)資料
| 型號： | TS8308500CG |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | 1.27 MM PITCH, HEAT SINK, CERAMIC, BGA-72 |
| 文件頁數(shù)： | 41/42頁 |
| 文件大?。?/td> | 641K |
| 代理商： | TS8308500CG |
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8
TS8308500
Preliminary Specification
ββββ-site
Parameter
Symb
Test
level
Min
Typ
Max
Unit
SWITCHING PERFORMANCE AND CHARACTERISTICS – See Timing Diagrams Figure 1, Figure 2
Maximum clock frequency
(Note 14)
FS
500
700
Msps
Minimum clock frequency
(Note 15)
FS
410
50
Msps
Minimum Clock pulse width (high)
TC1
4
1710
2
50
ns
Minimum Clock pulse width (low)
TC2
4
1710
2
50
ns
Aperture delay
(Note 2)
TA
4
100
+250
400
ps
Aperture uncertainty
(Notes 2, 5)
Jitter
4
0.4
0.6
ps (rms)
Data output delay
(Notes 2, 10, 11, 12)
TOD
4
1150
1360
1660
ps
Output rise/fall time for DATA (20 % – 80 %)
(note 11)
TR/TF
4
250
350
550
ps
Output rise/fall time for DATA READY
(20 % – 80 % )
(note 11)
TR/TF
4
250
350
550
ps
Data ready output delay
(Notes 2,10, 11, 12)
TDR
4
1110
1320
1620
ps
Data ready reset delay
TRDR
4
720
1000
ps
Data to data ready – clock low pulse width
(See timing diagram, notes 9, 13,14)
TOD-
TDR
4
0
40
80
ps
Data to data ready output delay (50% duty cycle)
(See timing diagram, notes 2, 15) @ 500 Msps
TD1
4
920
960
1000
ps
Data pipeline delay
TPD
4
clock
cycles
Note 1 : Differential output buffers are internally loaded by 75
resistors. Buffer bias current = 11 mA.
Note 2 : See definition of terms
Note 3 : Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS.
Note 4 : Output error amplitude <
± 4 LSB around worst code.
Note 5 :
Maximum jitter value obtained for single–ended clock input on the JTS8308500 die (chip on board) : 200 fs.
(500 fs expected on TS8308500)
Note 6 : Digital output back termination options depicted in Application Notes figures 3,4,5 .
Note 7 : With a typical value of TD = 465 ps, at 500 Msps, the timing safety margin for the data storing using the ECLinPS 10E452 output
registers from Motorola is of
± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR, DRB).
Note 8 : The clock inputs may be indifferently entered in differential or single–ended, using ECL levels or 4 dBm typical power level into the
50
termination resistor of the inphase clock input.
(4 dBm into 50
clock input correspond to 10 dBm power level for the clock generator.)
Note 9 : At 500 MSPS, 50/50 clock duty cycle, TC2 = 1 ns (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate.
Note 10 : Specified loading conditions for digital outputs :
- 50
or 75 controlled impedance traces properly 50 / 75 terminated, or unterminated 75 controlled impedance traces.
- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola.( e.g. : 10E452 ) ( Typical input parasitic
capacitance of 1.5 pF including package and ESD protections. )
Note 11 : Termination load parasitic capacitance derating values :
- 50
or 75 controlled impedance traces properly 50 / 75 terminated : 60 ps / pF or 75 ps per additional ECLinPS load.
- Unterminated ( source terminated ) 75
controlled impedance lines : 100 ps / pF or 150 ps per additional ECLinPS termination
load.
Note 12 : apply proper 50 / 75
impedance traces propagation time derating values : 6 ps / mm (155 ps/inch) for TSEV8308500 Evaluation
Board.
Note 13 : Values for TOD and TDR track each other over temperature, (1 % variation for TOD - TDR per 100
oC temperature variation).
Therefore TOD - TDR variation over temperature is negligible. Moreover, the internal (onchip ) and package skews between each Data
TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps
apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about TOD - TDR variation over
temperature in section 7).
Note 14 : Min value guarantees performance. Max value guarantees functionality.
Note 15 : Min value guarantees functionality. Max value guarantees performance.
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