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參數(shù)資料
| 型號： | TS8387MF |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 34/38頁 |
| 文件大?。?/td> | 617K |
| 代理商： | TS8387MF |
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TS8387
5/38
3.3.
ELECTRICAL OPERATING CHARACTERISTICS
VEE = DVEE = –5 V ; VCC = +5 V ; VIN –VINB = 500 mVpp Full Scale differential input ;
Digital outputs 75 or 50
W differentially terminated ; Tj (typical) = 70°C. Full temperature range : –55 < Tc ; Tj < +125
Parameter
Symb
Temp
Test
level
Min
Typ
Max
Unit
RESOLUTION
8
bits
ANALOG INPUTS
Full Scale Input Voltage range (differential mode)
( 0 Volt common mode voltage )
VIN
VINB
Full
IV
–125
125
mV
Full Scale Input Voltage range (single-ended input
option ) (see Application Notes)
VIN
VINB
Full
IV
–250
0
250
mV
Analog input capacitance
CIN
IV
3
pF
Input bias current
IIN
IV
10
mA
Input Resistance
RIN
IV
1
M
W
Full Power input Bandwidth
FPBW
IV
1.2
GHz
CLOCK INPUTS
Logic compatibility for clock inputs
( note 7 )
(see Application Notes)
ECL or specified clock
input power level in dBm
ECL Clock inputs voltages (VCLK or VCLKB) :
H Logic ”0” voltage
VIL
Full
–1.5
V
H Logic ”1” voltage
VIH
Full
–1.1
V
H Logic ”0” current
IIL
Full
5
mA
H Logic ”1” current
IIH
Full
5
mA
Clock input power level into 50 ohms termination
dBm into 50 ohms
Clock input power level
4
10
dBm
Clock input capacitance
CCLK
3
pF
DIGITAL OUTPUTS (
notes 1,6)
Logic compatibility for digital outputs
(see Application Notes)
ECL or low voltage dif-
ferential output signals
Differential output voltage swings :
H 75 W open transmission lines ( ECL levels )
H 75 W differentially terminated
H 50 W differentially terminated
1.620
0.825
0.660
V
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相關代理商/技術參數(shù) |
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|---|---|
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| TS8388BCFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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