- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄225343 > TS87C51RB2-EED (ATMEL CORP) 8-BIT, OTPROM, MICROCONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號： | TS87C51RB2-EED |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, MICROCONTROLLER, PQFP44 |
| 封裝： | 1.40 MM HEIGHT, VQFP-44 |
| 文件頁數(shù)： | 39/74頁 |
| 文件大小： | 689K |
| 代理商： | TS87C51RB2-EED |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
44
Rev. C - 06 March, 2001
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
6.8. Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.
In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to
be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or
during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running,
the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
6.9. Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to Table 17., PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last
instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.
VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from
power-down. To properly terminate power-down, the reset or external interrupt should not be executed before VCC
is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled
and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 17.
When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power
down exit will be completed when the first input will be released. In this case the higher priority interrupt service
routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction
that put TS80C51Rx2 into power-down mode.
Figure 17. Power-Down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect
the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt,
PD and IDL bits are cleared and idle mode is not entered.
INT1
INT0
XTAL1
Power-down phase
Oscillator restart phase
Active phase
相關PDF資料 |
PDF描述 |
|---|---|
| TS87C51RD2-VIBD | 8-BIT, OTPROM, 40 MHz, MICROCONTROLLER, PQCC44 |
| TSA5526MDK-T | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| TSB100008DS | 40 A, BARRIER STRIP TERMINAL BLOCK |
| TSB200002 | 65 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB23011DS | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TS87C51RB2-EER | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| TS87C51RB2-LCA | 功能描述:IC MCU 8BIT 16K OTP 30MHZ 40-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:87C 標準包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設備:POR，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（32K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉換器:- 振蕩器型:內部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| TS87C51RB2-LCAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TS87C51RB2-LCB | 功能描述:IC MCU 8BIT 16K OTP 30MHZ 44PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:87C 標準包裝:1,500 系列:AVR® ATtiny 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，LIN，SPI，UART/USART，USI 外圍設備:欠壓檢測/復位，POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):16 程序存儲器容量:8KB（4K x 16） 程序存儲器類型:閃存 EEPROM 大小:512 x 8 RAM 容量:512 x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉換器:A/D 11x10b 振蕩器型:內部 工作溫度:-40°C ~ 125°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:帶卷 (TR) |
| TS87C51RB2-LCBB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復。