參數(shù)資料
型號(hào): TSA1005-40IF
元件分類: ADC
英文描述: Analog to Digital Converter
中文描述: 模數(shù)轉(zhuǎn)換器
文件頁數(shù): 2/19頁
文件大?。?/td> 194K
代理商: TSA1005-40IF
TSA1005-40
2/19
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=10.13MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V
Tamb = 25
°
C (unless otherwise specified)
DYNAMIC CHARACTERISTICS
TIMING CHARACTERISTICS
TIMING DIAGRAM
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
SFDR
Spurious Free Dynamic Range
-73
dBc
SNR
Signal to Noise Ratio
59
dB
THD
TotalHarmonics Distortion
-73
dBc
SINAD
Signal to Noise and Distortion Ratio
58.5
dB
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
FS
Sampling Frequency
0.5
40
MHz
DC
Clock Duty Cycle
45
50
55
%
TC1
Clock pulse width (high)
12.5
ns
TC2
Clock pulse width (low)
12.5
ns
Tod
Data Output Delay (Clock edge to Data Valid)
10pF load capacitance
5
ns
Tpd I
Data Pipeline delay for I channel
7
cycles
Tpd Q
Data Pipeline delay for Q channel
7.5
cycles
Ton
Falling edge of OEB to digital output valid data
1
ns
Toff
Rising edge of OEB to digital output tri-state
1
ns
N-1
N
N+1
N+6
N+7
N+2
N+5
N+3
N+4
N+8
CLK
TpdI + Tod
N+9
N+10
N+11
N+12
N+13
DATA
OUTPUT
sample N+1
I channel
sampleN
Q channe
sample N+1
Q channel
sampleN+2
I channel
sample N+2
Q channel
sampleN+3
I channe
OEB
Simultaneous sampling
on I/Q channels
SELECT
sampleN-9
I channel
sampleN-8
I channel
sampleN-7
Q channel
sampleN-6
Q channel
CLOCKAND SELECTCONNECTED TOGETHER
Tod
I
Q
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