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參數(shù)資料
| 型號： | TSA5059T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-102, SOT-109-1, SOP-16 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 151K |
| 代理商： | TSA5059T |
1999 Oct 05
10
Philips Semiconductors
Preliminary specification
2.7 GHz I
2
C-bus controlled low phase
noise frequency synthesizer
TSA5059
XT/COMP frequency output
It is possible to output either the crystal or the comparison
frequency at this pin to be used in the application, for
example to drive a second PLL synthesizer, saving a
quartz crystal in the bill of material. To output f
xtal
, it is
necessary to set bit XCE to logic 1 and bit XCS to logic 0,
or bit XCE to logic 0 and bit XCS to logic 1 during a test
mode, while to output f
comp
, it is necessary to set both
bits XCE and XCS to logic 1.
If the output signal at this pin is not used, it is
recommended to disable it, setting both bits XCE and XCS
to logic 0. Table 10 shows how this pin is programmed.
At power-on, the XT/COMP output is set, with the f
xtal
signal selected.
Prescaler enable
Even if the TSA5059 is able to work with the relation
f
comp
= step size for an input frequency up to 2.7 GHz, this
ICisdesigned tobebackward compatiblewith existingICs
for which this relation is only valid for an RF frequency up
to 2.0 GHz and in which it is necessary to select a fixed
divide-by-two prescaler for frequencies between 2.0 and
2.7 GHz.
The prescaler is selected by setting bit PE to logic 1 and
it is not in use if bit PE is set to logic 0.
For new designs, and especially if it is important to reach
a low phase noise on the controlled VCO, it is
recommended to set bit PE to logic 0, and not to use the
prescaler, allowing the comparison frequency to be equal
to the step size, whatever the RF frequency is between
64 and 2700 MHz.
Test modes
It is possible to access the test modes setting bit XCE to
logic 0 and bit XCS to logic 1. One specific test mode is
then selected using bits T2, T1 and T0, as described in
Table 10.
Table 10
XT/COMP and test mode selection; note 1
Notes
1.
2.
X = don’t care.
Status at Power-on reset.
XCE
XCS
T2
T1
T0
XT/COMP OUTPUT
TEST MODE
0
1
1
0
0
0
1
1
X
X
X
0
X
X
X
0
X
X
X
0
disabled
f
xtal
f
comp
f
xtal
normal operation
normal operation
normal operation
test operation: charge pump sink;
status byte: bit FL = 1
test operation: charge pump source;
status byte: bit FL = 0
test operation: charge pump disabled;
status byte: bit FL = 0
test operation:
1
2
f
DIV
switched to Port P0
test operation: tuning voltage (pin VT) is
off (high-impedance); note 2
0
1
0
0
1
f
xtal
0
1
0
1
0
f
xtal
0
0
1
1
0
1
1
X
1
X
f
xtal
f
xtal
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TSA5059TS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5060A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5060AT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5060AT/C1,518 | 功能描述:IC SYNTH FREQ 1.3GHZ 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| TSA5060AT/C2,118 | 制造商:NXP Semiconductors 功能描述: |
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