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參數(shù)資料
| 型號： | TSA5059TS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 151K |
| 代理商： | TSA5059TS |
1999 Oct 05
7
Philips Semiconductors
Preliminary specification
2.7 GHz I
2
C-bus controlled low phase
noise frequency synthesizer
TSA5059
Table 2
Explanation of Table 1
Address selection
(see Table 3)
The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having
up to 4 synthesizers in one system. The relationship between MA1 and MA0 and the input voltage at pin AS is given in
Table 3.
Table 3
Address selection
Note
1.
This address is selected by connecting a 15 k
resistor between pin AS and pin V
CC
.
Status at Power-On Reset (POR)
At power-on or when the supply voltage drops below approximately 2.75 V, internal registers are set according to
Table 4.
Table 4
Status at Power-on reset; note 1
Notes
1.
2.
X = don’t care.
At Power-on reset, all output ports are in high-impedance state.
BIT
DESCRIPTION
MA1 and MA0
A
N16 to N0
PE
R3 to R0
C1 and C0
XCE
XCS
T2, T1 and T0
P3, P2 and P1
P0
programmable address bits; see Table 3
acknowledge bit
programmable main divider ratio control bits; N = N16
×
2
16
+ N15
×
2
15
+ ... + N1
×
2
1
+ N0
prescaler enable (prescaler by 2 is active when bit PE = 1)
programmable reference divider ratio control bits; see Table 8
charge pump current select bits; see Table 9
XT/COMP enable; XT/COMP output active when bit XCE = 1; see Table 10
XT/COMP select; signal select when bit XCE = 1, test mode enable when bit XCE = 0; see Table 10
test mode select when bit XCE = 0 and bit XCS = 1; see Table 10
Port P3, P2 and P1 output states
Port P0 output state, except in test mode; see Table 10
MA1
MA0
VOLTAGE APPLIED TO PIN AS
0
0
1
1
0
1
0
1
0 to 0.1V
CC
open-circuit
0.4V
CC
to 0.6V
CC
; note 1
0.9V
CC
to V
CC
BYTE
DESCRIPTION
MSB
LSB
CONTROL BIT
1
2
3
4
5
address
programmable divider
programmable divider
control data
control data
1
0
X
1
0
1
X
X
X
0
0
X
X
X
0
0
X
X
X
1
0
X
X
X
MA1
X
X
X
1
(2)
MA0
X
X
X
X
(2)
0
X
X
X
A
A
A
A
A
X
(2)
X
(2)
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| TSA5059 | 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
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