參數(shù)資料
型號(hào)： TSA5515T
廠商： NXP SEMICONDUCTORS
元件分類： XO, clock
英文描述： 1.3 GHz bi-directional I2C-bus controlled synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO14
封裝： PLASTIC, SO-14
文件頁(yè)數(shù)： 6/15頁(yè)
文件大小： 117K
代理商： TSA5515T
November 1991
6
Philips Semiconductors
Product specification
1.3 GHz bi-directional I
2
C-bus controlled synthesizer
TSA5515T
FUNCTIONAL DESCRIPTION
The TSA5515T is controlled via the two-wire I
2
C-bus. For
programming, there is one module address (7 bits) and the
R/W bit for selecting READ or WRITE mode.
WRITE mode:
R/W = 0 (see Table
1
)
After the address transmission (first byte), data bytes can
be sent to the device. Four data bytes are needed to fully
program the TSA5515T. The bus transceiver has an
auto-increment facility, which permits the programming of
the TSA5515T within one single transmission
(address + 4 data bytes).
The TSA5515T can also be partly programmed on the
condition that the first data byte following the address is
byte 2 or byte 4. The meaning of the bits in the data bytes
is given in Table 1. The first bit of the first data byte
transmitted indicates whether frequency data (first bit = 0)
or charge pump and port information (first bit = 1) will
follow. Until an I
2
C-bus STOP condition is sent by the
controller, additional data bytes can be entered without the
need to re-address the device. This allows a smooth
frequency sweep for fine tuning. At power-on, the ports are
set to the high impedance state.
The 7.8125 kHz reference frequency is obtained by
dividing the output of the 4 MHz crystal oscillator by 512.
Because the input of the UHF/VHF signal is first divided by
8, the step size is 62.5 kHz. A 3.2 MHz crystal can offer a
step size of 50 kHz.
Table 1
Write data format
MA1, MA0 programmable address bits (see Table 3)
Note
1.
X = don’t care
MSB
LSB
Address
Programmable
divider
Programmable
divider
Charge-pump
and test bits
Output ports control
bits
1
0
1
0
0
0
MA1
N10
MA0
N9
0
A
A
byte 1
byte 2
N14
N13
N12
N11
N8
N7
N6
N5
N4
N3
N2
N1
N0
A
byte 3
1
CP
T1
T0
X
X
X
OS
A
byte 4
P7
X
X
X
X
P2
P1
X
A
byte 5
A
N14 to N0
N = N14
×
2
14
+N13
×
2
13
+...+N1
×
2
1
+N0
CP
CP = 0
CP = 1
P7, P2, P1 = 1
P7, P2, P1 = 0
T1, T0, OS = 0 0 0
T1 = 1, P2 = f
ref
, P7 = f
DIV
T0 = 1
OS = 1
acknowledge bit
programmable divider bits
charge-pump current
50
μ
A
220
μ
A
open-collector outputs are active
outputs are in high impedance state
normal operation
3-state charge-pump
operational amplifier output is switched off (varicap drive disable)
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