參數(shù)資料
型號(hào): TSA5515T
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: 1.3 GHz bi-directional I2C-bus controlled synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO14
封裝: PLASTIC, SO-14
文件頁(yè)數(shù): 7/15頁(yè)
文件大?。?/td> 117K
代理商: TSA5515T
November 1991
7
Philips Semiconductors
Product specification
1.3 GHz bi-directional I
2
C-bus controlled synthesizer
TSA5515T
READ mode:
R/W = 1 (see Table
2
)
Data can be read out of the TSA5515T by setting the R/W
bit to 1. After the slave address has been recognized, the
TSA5515T generates an acknowledge pulse and the first
data byte (status word) is transferred on the SDA line
(MSB first). Data is valid on the SDA line during a high
position of the SCL clock signal.
A second data byte can be read out of the TSA5515T if the
processor generates an acknowledge on the SDA line.
End of transmission will occur if no acknowledge from the
processor occurs. The TSA5515T will then release the
data line to allow the processor to generate a STOP
condition.
The POR flag (power-on-reset) is set to 1 when V
CC
goes
below 3 V and at power-on. It is reset when an end of data
is detected by the TSA5515T (end of a READ sequence).
Control of the loop is made possible with the in-lock flag
FL, which indicates (FL = 1) when the loop is
phase-locked.
Table 2
Read data format
Notes
1.
2.
POR
FL
power-on-reset flag. (POR = 1 on power-on)
in-lock flag (FL = 1 when the loop is phase-locked).
MSB is transmitted first.
Address selection (see Table
3
)
The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having several
synthesizers (up to 4) in one system. The relationship between MA1 and MA0 and the input voltage on AS input is given
in Table 3.
Table 3
Address selection
MSB
LSB
Address
Status byte
1
1
0
1
0
1
0
1
MA1
1
MA0
1
1
1
A
byte 1
byte 2
POR
FL
MA1
MA0
Voltage applied on AS pin
0
0
1
1
0
1
0
1
0 to 0.1 V
CC
open
0.4 to 0.6 V
CC
0.9 V
CC
to V
CC
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