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參數(shù)資料
| 型號： | TSA5520T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Fan Guard; For Use With:120mm Round Tubeaxial Fans; Fixing Centers:4.13"; Thickness:0.148" |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109, SO-16 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 285K |
| 代理商： | TSA5520T |
1996 Oct 10
8
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizer
TSA5520; TSA5521
3-wire bus mode (SW = open-circuit or V
CC1
);
see Figs 3
,
4 and 5
During a HIGH level on the CE input, the data is clocked
into the data register at the HIGH-to-LOW transition of the
clock pulse. The first four bits control the band switch
buffers and are loaded into the internal band switch
register on the 5th rising edge of the clock pulse.
The frequency bits are loaded into the frequency register
at the HIGH-to-LOW transition of the chip enable line when
an 18-bit or 19-bit data word is transmitted.
At power-on the charge-pump current is set to 280
μ
A, the
tuning voltage output is disabled (V
tune
= 33 V in
application; see Fig.12), the test bits T2, T1 and T0 are set
to the normal mode and RSB is set to 1 (TSA5520) or 0
(TSA5521). When an 18-bit data word is transmitted, the
most significant bit of the divider N14 is internally set to 0
and bit RSA is set to 1. When a 19-bit data word is
transmitted, bit RSA is set to 0.
When a 27-bit word is transmitted, the frequency bits are
loaded into the frequency register on the 20th rising edge
of the clock pulse and the control bits at the HIGH-to-LOW
transition of the chip enable line. In this mode, the
reference divider is given by the RSA and RSB bits (see
Table 7). The test bits T2, T1 and T0, the charge-pump
bit CP, the ratio select bit RSB and the OS bit can only be
selected or changed with a 27-bit transmission. They
remain programmed if an 18-bit or a 19-bit transmission
occurs. Only RSA is controlled by the transmission length
when the 18-bit or 19-bit format is used.
A data word of less than 18 bits will not affect the
frequency register of the device. The definition of the bits
is unchanged compared to the I
2
C bus mode.
The power-on detection threshold voltage V
POR
is fixed to
V
CC1
= 2 V at room temperature. Below this threshold, the
device is reset to the power-on state described above.
Table 6
Test bits
Table 7
Ratio select bits
T2
T1
T0
DEVICE OPERATION
0
0
1
1
1
1
0
1
1
1
0
0
1
X
0
1
0
1
normal mode
charge-pump is OFF
charge-pump is sinking current
charge-pump is sourcing current
f
ref
is available at LOCK output
1
2
f
div
is available at LOCK output
RSA
RSB
REFERENCE DIVIDER
X
0
1
0
1
1
640
1024
512
Fig.3 Normal mode; 18-bit data format (RSA = 1).
For TSA5520 bit RSB = 1 at power-on; the reference divider is 512 or 1024.
For TSA5521 bit RSB = 0 at power-on; the reference divider is 640.
For TSA5520/TSA5521 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains
as programmed with the 27-bit data word.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSA5521T | 1.3 GHz universal bus-controlled TV synthesizer |
| TSA5522 | 1.4 GHz I2C-bus controlled synthesizer |
| TSA5522M | 1.4 GHz I2C-bus controlled synthesizer |
| TSA5522T | 1.4 GHz I2C-bus controlled synthesizer |
| TSA5523M | Fan Finger Guard |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSA5520TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C-Bus Frequency Synthesizer |
| TSA5521 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizer |
| TSA5521M | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizer |
| TSA5521T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizer |
| TSA5521TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C-Bus Frequency Synthesizer |
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