參數(shù)資料
型號(hào)： TSA5522T
廠商： NXP SEMICONDUCTORS
元件分類： XO, clock
英文描述： 1.4 GHz I2C-bus controlled synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 1400 MHz, PDSO16
封裝： 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SOP-16
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 172K
代理商： TSA5522T
1996 Jan 23
6
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
FUNCTIONAL DESCRIPTION
The device is controlled via the two-wire I
2
C-bus. For
programming, there is one module address (7 bits) and the
R/W bit for selecting the READ or the WRITE mode.
I
2
C-bus mode
W
RITE MODE
(R/W = 0); see Table 1
Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are required to
fully program the device. The bus transceiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing
that the first data byte following the address is divider
byte 1 (DB1) or control byte (CB). The bits in the data
bytes are defined in Table 1. The first bit of the first data
byte transmitted indicates whether frequency data
(first bit = 0) or control and ports data (first bit = 1) will
follow. Until an I
2
C-bus STOP command is sent by the
controller, additional data bytes can be entered without the
need to re-address the device. The frequency register is
loaded after the 8th clock pulse of the second divider
byte (DB2), the control register is loaded after the 8th clock
pulse of the control byte (CB) and the ports register is
loaded after the 8th clock pulse of the ports byte (PB).
I
2
C-
BUS ADDRESS SELECTION
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage on the AS input.
The relationship between MA1 and MA0 and the input
voltage on the AS input is given in Table 3.
Table 1
I
2
C-bus data format
Note
1.
Not available on 16-pin devices.
Table 2
Description of Table 1
BYTE
MSB
DATA BYTE
LSB
COMMAND
Address byte (ADB)
Divider byte 1 (DB1)
Divider byte 2 (DB2)
Control byte (CB)
Ports byte (PB)
1
0
1
0
0
0
MA1
N10
N2
RSA
P2
MA0
N9
N1
RSB
P1
0
A
A
A
A
A
N14
N6
CP
P6
N13
N5
T2
P5
(1)
N12
N4
T1
P4
(1)
N11
N3
T0
X
N8
N0
OS
P0
N7
1
P7
(1)
SYMBOL
DESCRIPTION
MA1, MA0
N14 to N0
CP
T2 to T0
RSA, RSB
OS
programmable address bits (see Table 3)
programmable divider bits N = N14
×
2
14
+ N13
×
2
13
+ ... + N1
×
2 + N0
charge-pump current; CP = 0 = 50
μ
A; CP = 1 = 250
μ
A
test bits (see Table 4). For normal operation T2 = 0; T1 = 0; T0 = 1
reference divider ratio select bits (see Table 5)
tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON; when
OS = 1 tuning voltage is OFF (high impedance)
PNP band switch buffers control bits
NPN open collector control bits when P
n
= 0 output n is OFF; when P
n
= 1 output n is ON
don’t care
P2 to P0
P7 to P4
X
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